Core Viewpoint - ASML emphasizes the importance of High NA EUV technology for the future of semiconductor manufacturing, with significant advancements already being reported by major clients like Intel and Samsung [2][4]. Group 1: ASML and High NA EUV Technology - ASML confirmed revenue from a High NA EUV machine, which slightly lowered its gross margin but still resulted in a strong overall gross margin of 53.7% [2]. - Intel reported using High NA EUV equipment to expose over 30,000 wafers in a single quarter, significantly improving its process flow by reducing the number of steps from 40 to below 10 [2]. - Samsung noted a 60% reduction in cycle time for a specific layer using High NA EUV technology, indicating its faster maturity compared to earlier low NA EUV devices [2]. Group 2: Samsung's Investment in Next-Gen Lithography - Samsung is increasing its procurement of High NA EUV lithography machines to enhance its competitive edge in the 2nm GAA process, despite the high costs of these machines [4][5]. - The yield for Samsung's Exynos 2600 chip using this technology was reported at 30%, with a target of at least 70% for financial viability in mass production [5]. - Samsung aims to achieve mass production of 1.4nm nodes by 2027, actively evaluating the use of High NA EUV tools in its manufacturing processes [5]. Group 3: SK Hynix's Adoption of High NA EUV - SK Hynix has assembled the industry's first Twinscan NXE:5200B High NA EUV lithography system, which will initially serve as a development platform for next-gen DRAM technology [8][9]. - The new system is expected to enhance productivity and product performance by enabling more complex patterns on wafers, thus increasing chip density and power efficiency [8]. - SK Hynix plans to simplify existing EUV processes and accelerate the development of next-gen memory products, aiming to solidify its technological leadership in the market [9]. Group 4: Industry Perspectives on High NA EUV - Intel's future procurement of High NA EUV machines will depend on its wafer manufacturing strategy, with no immediate changes expected due to current challenges [12]. - TSMC has reiterated that its next-generation processes do not require High NA EUV systems, indicating a cautious approach towards adopting this technology [12][13]. - Micron plans to introduce EUV technology into DRAM production by 2025, with the timeline for High NA EUV adoption remaining uncertain [14]. Group 5: Future Considerations - Despite the high costs associated with High NA EUV machines, there is a growing recognition of their potential benefits in advanced chip manufacturing [16]. - Emerging transistor architectures like GAAFET and CFET may reduce reliance on advanced lithography tools, shifting focus towards etching technologies [16][17]. - The semiconductor industry is at a crossroads, with companies evaluating the balance between lithography and other critical manufacturing processes as they advance towards more complex chip designs [17].

Core Viewpoint - The GPU market is experiencing significant growth, particularly benefiting Nvidia, which has increased its market share to 94% as of the latest report from Jon Peddie Research [2][4]. Market Overview - The global PC-based graphics AIB market is projected to reach 11.6 million units by Q2 2025, reflecting a nearly 30% quarter-over-quarter growth [2]. - Data center GPU shipments also saw a quarter-over-quarter increase of 4.7% [2]. Competitive Landscape - Nvidia's dominance in the GPU market continues to strengthen, while AMD's market share has decreased by 2% to 6% [4]. - According to the latest Steam survey, Nvidia holds nearly 75% of the GPU market share, with 7 out of the top 13 performing GPUs in August being from the Blackwell RTX 5000 series [7]. Pricing Trends - There is a notable decline in prices for mid-range and entry-level AIBs, while high-end AIB prices are on the rise, with many retailers facing stock shortages [7][9]. - The overall AIB attach rate for desktop computers increased by 2.3% to 154%, indicating a strong demand for GPUs relative to CPU sales [7][11]. Future Outlook - Jon Peddie Research forecasts a compound annual growth rate (CAGR) of -5.4% for AIBs from 2024 to 2028, with an estimated installed base of 163 million units by the end of the forecast period [9]. - The anticipated release of the RTX 5000 series in early 2025 and the potential launch of Super versions by the end of this year may influence market dynamics [10]. Consumer Behavior - Despite challenges, gamers appear willing to invest in upgrading their systems, contributing to the increased attach rate of GPUs [11]. - Concerns over tariffs and potential import taxes on semiconductor products are influencing consumer purchasing behavior [11].

公众号记得加星标⭐️，第一时间看推送不会错过。 来源 ：内容 编译自 photonics 。 植根于经典精密机械的光学和由微电子小型化定义的半导体（曾经是截然不同的行业，如今在创新的 前沿日益重叠。这种融合并非巧合。相反，它是共同的技术挑战和制造技术相互融合的结果，部分原 因是光学元件的要求超越了传统加工方法的极限。为了满足这些严格的要求，制造商越来越多地采用 最初为半导体制造工艺建立的技术。 日益增多的应用需要兼顾两个领域的优势，这是这一蓬勃发展的重叠领域的另一个决定性因素。半导 体制造是工艺标准化、材料创新和纳米级精度的既定驱动力。如今，随着这些能力向光学制造领域前 沿发展，制造商们正在将其应用于开发解决方案。这些解决方案涵盖了从太空望远镜的自由曲面透镜 到光子集成电路 (PIC) 中的纳米结构表面——这些解决方案作为可扩展的高性能电信和高级数据处理 解决方案，正日益受到青睐。 此外，自适应光学和元光学正在重新定义光束控制和波前整形，能够在紧凑的外形尺寸内以前所未有 的精度实现光的动态控制。 半导体与精密光学之间界限的模糊在材料和技术方面也显而易见。例如，传统上用于电力电子和恶劣 及极端环境应用的碳化硅 ...

Core Viewpoint - The Taiwanese silicon carbide (SiC) industry is experiencing rapid growth due to increasing demand from Nvidia for advanced GPU performance, despite challenges in the global SiC supply chain [3][4]. Group 1: Industry Developments - Wolfspeed, a global leader in SiC, declared bankruptcy in May, while Taiwan's GlobalWafers announced plans to develop new SiC products with clients [3]. - The shift from silicon to silicon carbide for interposer layers in advanced semiconductor processes is being driven by Nvidia's new Rubin processor, which aims to enhance performance [3][4]. - The advanced chip plans are expected to handle power levels up to 1000 volts, significantly higher than Tesla's fast charging voltage of 350 volts [4]. Group 2: Technical Insights - Nvidia's NVLink technology benefits from closer GPU and memory proximity, leading to faster data transfer and improved power efficiency, making SiC an attractive material due to its superior thermal conductivity [4]. - The transition to SiC interposer layers requires advanced cutting techniques, as SiC's hardness is comparable to diamond, and poor cutting can lead to unusable surfaces [4][5]. - The production of larger single-crystal SiC wafers is a key differentiator for Taiwanese manufacturers compared to Chinese competitors, who primarily produce 6-inch and 8-inch wafers [4]. Group 3: Future Outlook - TSMC is collaborating with global manufacturers to develop SiC interposer manufacturing technology, while new laser cutting machines are being developed by companies like DISCO [5]. - Nvidia's first-generation Rubin GPU will still use silicon interposer layers until the new cutting equipment is available, with SiC expected to be integrated into advanced packaging by the end of 2025 [5].

Core Viewpoint - Chiplet technology is a method to meet the growing demands for computing power and I/O bandwidth by splitting SoC functions into smaller heterogeneous or homogeneous chips, integrated into a single system-in-package (SIP) [1] Group 1: System Partitioning - Design teams must consider which functional blocks to include and how to partition these functions across different chipsets, while also selecting the most efficient semiconductor process node for each functional block [2] - Common high-level partitioning schemes may involve separating compute chips, I/O chips, and storage functions into different chipsets, weighing factors like latency, bandwidth, and power consumption based on the chosen process nodes and partitioning [2] Group 2: Process Node Selection - In the latest process nodes, AI accelerators may be ideal for optimizing performance and power, but implementing cache at this node may not be efficient; SRAM is better implemented at lower-cost nodes [3] - A 3D implementation can be considered, where compute chips are on the latest node and SRAM and I/O are on older nodes, exemplified by AMD's Ryzen 7000X3D processor with second-generation 3D V-Cache [3] Group 3: Chip-to-Chip Connection Considerations - UCIe has become the de facto standard for die-to-die connections, with design teams needing to understand bandwidth requirements based on workload, including both data and control bandwidth [4] - Designers have various options for data rates and configurations, needing to balance data rates (ranging from 16G to 64G) and the number of channels to meet chip constraints [4] Group 4: Advanced Packaging Challenges - The focus on packaging technology has intensified, presenting both opportunities and challenges in multi-chip designs [6] - Designers must decide how to interconnect chips in multi-die designs, with considerations for cost, design speed, and interconnect density [6][7] Group 5: Testing and Security Design - Testing planning involves wafer probing to provide known good die (KGD) and using protocols like IEEE 1838 for accessing chips that may not be directly accessible [9] - Security design considerations arise with IP integration, requiring authentication features and potential support for secure computing architectures to protect sensitive data [10]

公众号记得加星标⭐️，第一时间看推送不会错过。 来源 ：内容 编译自 yole 。 由于传统的基于处理器的架构面临物理限制，这项技术在满足数据中心需求（尤其是人工智能和机器 学习）方面发挥着至关重要的作用。硅光子学实现的高速通信对于支持更快的计算至关重要。不断增 长的带宽需求不仅推动了硅光子学的发展，也推动了薄膜铌酸锂的发展，从而提升了网络的数据容 量。 光子集成电路，尤其是绝缘体上硅 (SOI) 和绝缘体上铌酸锂 (LNOI)，为具有高容量可扩展性的应用 提供了多功能平台，尤其适用于数据中心，而中国企业正在成为该领域的新领导者。由于硅片性能稳 定，电信是另一个高容量应用领域。除此之外，光学激光雷达、3D 集成、量子计算、光学陀螺仪， 甚至医疗光子学都拥有巨大的潜力，尽管一些应用面临技术和监管挑战。硅光子学向可见光谱的扩展 有望在未来开启更多创新用途。 硅光子产业格局正在围绕多元化参与者形成：积极参与硅光子产业的主要垂直整合参与者（例如 Innolight、思科、Marvell、Broadcom、Coherent、Lumentum、Eoptolink）；初创公司 / 设计公 司 （ Xphor 、 DustP ...

公众号记得加星标⭐️，第一时间看推送不会错过。 人工智能革命催生了对训练前沿模型的处理能力的巨大需求，而英伟达正用其高端 GPU 来满足这一 需 求 。 然 而 ， 2025 年 人 工 智 能 突 然 转 向 推 理 和 代 理 人 工 智 能 ， 暴 露 出 内 存 管 道 方 面 的 缺 口 ， d- Matrix 希望通过其创新的 3D 堆叠数字内存计算 (3DIMC) 架构来解决这个问题，该架构已于上周在 Hot Chips 大会上进行了展示。 该公司由首席执行官 Sid Sheth 和首席技术官 Sudeep Bhoja 于 2019 年创立，两人均曾担任高速互 连开发商 Inphi Corp 的高管，该公司于 2020 年被 Marvell 以 100 亿美元收购。其目标是开发内存 计 算 芯 片 级 技 术 ， 为 AI 推 理 带 来 比 传 统 DRAM 带 宽 更 大 的 内 存 ， 且 成 本 远 低 于 高 带 宽 内 存 (HBM)。 Sheth 在领英上发帖称："我们相信，AI 推理的未来不仅取决于对计算的重新思考，也取决于对内存 本身的重新思考。我们正在为新的内存计算范式 (3 ...

第六代（6G）无线技术距离现实又近了一步，有消息称中国研究人员发布了全球首款"全频"6G 芯片。该芯片能够提供超过每秒100千兆比特（Gbps）的移动互联网速度，由北京大学和香港 城市大学的科学家领导的团队开发。 6G技术是5G的继承者，有望带来我们通信方式的巨大飞跃。它将带来诸多优势，例如超高速连接、 超低延迟以及能够实时管理和优化网络的AI集成。为了实现这些优势，6G网络需要运行在一系列频 率范围内，从标准微波到频率更高的太赫兹波。当前的5G技术使用的无线电频率有限，与前几代无 线技术类似。 公众号记得加星标⭐️，第一时间看推送不会错过。 这款新芯片尺寸仅为11毫米 x 1.7毫米，大小与拇指指甲差不多。它的工作频率范围很广，从0.5 GHz到115 GHz，而传统上需要九个独立的无线电系统才能覆盖这个频谱。 研究人员在发表于《自然》杂志的论文中评论道："我们提出的系统代表着向未来全频谱、全场景无 线网络迈出了显著的一步。与之前的光子辅助无线演示相比，这实现了可重构的全链路无线通信，并 具有更高的带宽、数据速率和系统功能。" 该团队的主要创新之一是将无线系统的所有重要部件封装到一个由薄膜铌酸锂（TFLN） ...

Core Viewpoint - The introduction of Backside Power Delivery Network (BSPDN) by major semiconductor companies like Intel and TSMC is a significant advancement in semiconductor technology, aimed at addressing the limitations of traditional chip designs and extending Moore's Law [2][4]. Group 1: What is Backside Power Delivery? - BSPDN is considered a breakthrough that continues Moore's Law, improving heat dissipation, reducing IR drop, and increasing chip density [4]. - Traditional chip designs concentrate power and signal lines on the front of the wafer, which becomes problematic as advanced processes approach 2nm and below [5]. Group 2: Importance of Backside Power Delivery - Reduces voltage drop and power loss, ensuring stable power supply during high-speed AI computations and server applications [6]. - Addresses thermal bottlenecks and IR drop issues caused by lengthy circuits, which can lead to operational errors or performance degradation [7]. - Enhances performance by separating power and signal, thereby reducing interference [8]. Group 3: Global Strategies for Backside Power Delivery - Three main solutions are currently being developed: imec's Buried Power Rail, Intel's PowerVia, and TSMC's Super Power Rail [10]. - imec is a leader in BSPDN technology, having published its findings in collaboration with Arm in 2022, utilizing BPR and nTSV architecture [11]. - Intel plans to implement BSPDN in its 18A process, expected to enter mass production in late 2025, focusing on complete separation of power and signal [11]. - Samsung will introduce BSPDN technology in its SF2Z process, with mass production anticipated in 2027 [12]. - TSMC's approach involves using Super Power Rail to direct power to the front transistors, which is crucial for maintaining its competitive edge in advanced processes [13]. Group 4: Implications for the Semiconductor Industry - BSPDN is seen as a key technology for extending Moore's Law, especially as traditional methods of shrinking transistors face limitations [15]. - The competition among major players to mature and commercialize this technology will determine their influence in the semiconductor industry over the next decade [13].

Core Viewpoint - The U.S. government has revoked TSMC's authorization to freely ship necessary equipment to its Nanjing plant in mainland China, potentially limiting the production capacity of this mature process chip factory [2][3] Group 1: Impact on TSMC - TSMC confirmed it received notification from the U.S. government that its "Verified End Use" (VEU) authorization for the Nanjing plant will be revoked by December 31 of this year, and the company is assessing the situation and taking appropriate measures [2][3] - The Nanjing plant, which initially focused on 16 to 12nm processes, has shifted to expanding 28nm capacity due to tightening U.S. export controls, with a monthly capacity of 20,000 wafers for 16/12nm and 40,000 wafers for 28/22nm [3][5] - The Nanjing plant generated approximately NT$26 billion in profit for TSMC last year, making it an important source of revenue despite its relatively low contribution percentage [3] Group 2: Broader Industry Implications - The U.S. actions highlight its influence over the electronic component supply chain, even affecting non-U.S. companies operating overseas [4][5] - The shift from blanket approvals to individual license applications creates uncertainty regarding the timeline for obtaining necessary permits for semiconductor operations in mainland China [5] - U.S. officials are reportedly working on solutions to alleviate bureaucratic burdens and expedite the processing of license applications, which have accumulated significantly [5]