北京大学FFET技术，开创全球三维集成新篇章

Core Viewpoints - The semiconductor industry is transitioning from traditional 2D planar integration to 3D integration to overcome physical and process limitations, aiming for higher density, lower power consumption, and higher efficiency [1] - FFET (Flip FET) technology, proposed by Peking University's Huang Ru team, represents a breakthrough in 3D integration by enabling dual-side active regions and interconnects, offering unprecedented design flexibility and integration density [2][9] - Advanced logic nodes, particularly 7nm and below, are driving semiconductor growth, with a projected CAGR of 27% from 2022 to 2026, and AI GPU/ASIC shipments expected to grow at a 42% CAGR [3] - FFET technology achieves a 12% reduction in SRAM area and a 21.5% frequency improvement under equal power consumption compared to CFET, pushing the limits of scaling to 2.5T [13][14] Advanced Logic Manufacturing Evolution - The evolution of transistor structures from planar MOSFET to FinFET and GAA (Gate-All-Around) has been driven by the need for better performance, density, and power efficiency [3] - GAA technology, which wraps the channel with gates on all sides, is set to be introduced by major players like TSMC at the 2nm node by 2025, marking the industry's entry into the GAA era [3] - Peking University has been a pioneer in GAA research, publishing the first domestic GAA paper in 2007 and establishing a complete technology chain from basic research to device design [4] 3D Integration Challenges and Innovations - Traditional 2D integration methods face physical bottlenecks, making transistor-level 3D integration the inevitable path for future logic node advancements [5] - CFET (Complementary FET) technology, developed by IMEC, represents a significant step in 3D integration but faces challenges in manufacturing complexity and interconnect limitations [6] - Backside Power Delivery Network (BSPDN) technology, adopted by Intel, Samsung, and TSMC, addresses interconnect congestion by placing power delivery on the chip's backside, though it requires advanced thinning and alignment techniques [7] FFET Technology and Its Advantages - FFET introduces a novel dual-side active region and interconnect design, allowing for more compact integration and reducing SRAM area by 12% compared to CFET [9][13] - The FFET process simplifies manufacturing by using a flip-and-bond approach, enabling self-aligned dual-side transistor construction without the need for high-aspect-ratio processes [10][11] - FFET's dual-side interconnect design enhances signal and power routing efficiency, reducing parasitic capacitance and resistance, leading to faster and more energy-efficient transistor operation [11][12] Future Directions: F3D and Beyond - FFET's derivative technology, Flip 3D (F3D), extends 3D integration by enabling multi-layer stacking on both sides of the wafer, offering new possibilities for high-performance computing and memory integration [15][16] - F3D supports dual-side hybrid bonding, reducing signal delay and improving data transmission speed and energy efficiency, making it superior to traditional Monolithic 3D (M3D) integration [16][17] - The FFET and F3D technologies are likened to urban planning, where the transition from 2D to 3D integration mirrors the evolution from flat cities to multi-layered, high-efficiency urban structures [18]