Nano Labs Launches FPU3.0 ASIC Design Architecture with 3D DRAM Stacking for AI and Blockchain Innovation

Core Insights - Nano Labs Ltd has launched the FPU3.0 architecture, which significantly enhances AI inference and blockchain performance, featuring advanced 3D DRAM stacking technology that provides a fivefold increase in power efficiency compared to the previous FPU2.0 architecture [7]. Company Overview - Nano Labs Ltd is a leading fabless integrated circuit design company in China, focusing on high throughput computing (HTC) chips, high performance computing (HPC) chips, and various advanced computing solutions [8]. - The company has developed a comprehensive flow processing unit (FPU) architecture that integrates features of both HTC and HPC, showcasing its commitment to innovation in the semiconductor industry [8]. Technology and Innovation - The FPU3.0 architecture incorporates stacked 3D memory with a theoretical bandwidth of 24TB/s and an upgraded Smart-NOC on-chip network, which supports a mix of compute cores and various traffic types [1]. - The modular design of the Nano FPU architecture allows for rapid product iteration by updating the FPU core IP while reusing or upgrading other modules as needed, facilitating the introduction of new features [10]. Market Applications - The FPU series of ASIC chips are optimized for high-bandwidth High Throughput Computing (HTC) applications, increasingly utilized in AI inference, edge AI computing, and data processing under 5G networks [2].