Arteris Addresses Silicon Design Reuse Challenge with New Magillem Packaging Product for IP Blocks and Chiplets

Core Insights - Arteris, Inc. has launched Magillem Packaging, a software product aimed at simplifying and accelerating the chip design process for advanced applications such as AI data centers and edge devices [1][2] Company Overview - Arteris is a leader in system IP for semiconductors, focusing on enhancing the creation of high-performance and power-efficient silicon [6] - The company provides network-on-chip (NoC) interconnect IP and SoC integration automation software, utilized by top semiconductor and technology firms to improve performance and reduce costs [6] Product Features - Magillem Packaging automates the assembly and reuse of existing technology, addressing the complexities of modern chip design, which includes a growing number of silicon IP blocks and tighter timelines [2][3] - The software is based on the IEEE 1685 (IP-XACT) standard, ensuring compatibility with industry tools and silicon IP, which helps in reducing errors and delays during the design process [3][7] - It allows IP teams to package and prepare hundreds or thousands of components for integration into chiplets or SoCs, enhancing productivity and speeding up technology delivery [3] Industry Impact - The introduction of Magillem Packaging is expected to address integration challenges in semiconductor design, driven by the increasing complexity of chip designs and the rapid growth of chiplets [3] - Companies like Andes Technology and MIPS have recognized the value of Magillem Packaging in optimizing IP packaging and integration, which aligns with the industry's need for faster and more reliable SoC development [5]