Core Insights - Marvell Technology, Inc. has introduced the industry's first 2nm 64 Gbps bi-directional die-to-die (D2D) interconnect, which significantly enhances bandwidth and performance for next-generation XPUs while minimizing power consumption and silicon area [1][4] Technology Advancements - The 64 Gbps bi-directional D2D interface offers a bandwidth density exceeding 30 Tbps/mm, which is more than three times that of UCIe at equivalent speeds, and reduces compute die area requirements by 15% compared to conventional implementations [2] - The interface features advanced adaptive power management that can lower power consumption by up to 75% under normal workloads and 42% during peak traffic periods [2][6] - Unique features such as redundant lanes and automatic lane repair enhance performance and reliability, improving yield and reducing bit-error rates [3] Strategic Positioning - Marvell's introduction of the 64 Gbps D2D interface aligns with its strategy to develop a comprehensive portfolio of technologies aimed at accelerating the development of custom devices and diversifying options for semiconductor designers [4] - The company has a proven track record of delivering industry firsts, including the announcement of a 2nm platform in March 2024 and the demonstration of working 2nm silicon by March 2025 [4] Custom Platform Strategy - Marvell's custom platform strategy focuses on delivering breakthrough results through unique semiconductor designs and innovative approaches, combining expertise in system and semiconductor design with a comprehensive portfolio of semiconductor solutions [5]
Marvell Unveils Industry's First 64 Gbps/wire Bi-Directional Die-to-Die Interface IP in 2nm to Power Next Generation XPUs