Synopsys Collaborates with TSMC to Drive the Next Wave of AI and Multi-Die Innovation

Core Insights - Synopsys, Inc. is collaborating closely with TSMC to deliver advanced EDA and IP products that support TSMC's leading-edge processes and packaging technologies, particularly in AI chip and multi-die design [2][3] - The partnership has resulted in multiple customer tape-outs, showcasing the effectiveness of the 3DIC Compiler platform and the comprehensive IP portfolio optimized for TSMC's advanced technologies [2][3] Collaboration and Innovation - Synopsys has made certified digital and analog flows available on TSMC's N2P and A16 processes, utilizing TSMC NanoFlex architecture to optimize performance and power [3][4] - The collaboration includes robust automotive IP solutions for TSMC N5A and N3A processes, ensuring high safety, security, and reliability while maximizing performance [3][4] Technology Advancements - The 3DIC Compiler platform supports advanced 3D stacking and CoWoS packaging technologies, enabling multiple customer tape-outs and enhancing productivity [6][7] - An AI-optimized photonic flow for TSMC-COUPE technology has been developed to improve system performance and address multi-wavelength and thermal requirements [7][8] IP Portfolio and Market Impact - Synopsys offers the industry's broadest IP portfolio optimized for low power on TSMC N2/N2P processes, which accelerates the path to silicon success and reduces integration risk [4][8] - The IP portfolio supports high-performance standards, including HBM4, 1.6T Ethernet, UCIe, PCIe 7.0, and UALink, catering to automotive, IoT, and HPC applications [8] Verification and Design Flow - Synopsys IC Validator signoff physical verification solution is certified for TSMC A16 process, enhancing DRC and LVS checking capabilities [5] - Ongoing collaboration on design flow development for TSMC's A14 process is expected to yield its first process design kit release in late 2025 [3][5]