Cadence Partners with TSMC to Power Next-Generation Innovations Using AI Flows and IP for TSMC Advanced Nodes and 3DFabric

Core Insights - Cadence has announced significant advancements in chip design automation and intellectual property (IP), leveraging its long-standing partnership with TSMC to enhance design infrastructure and expedite time to market for AI and high-performance computing (HPC) applications [2][4][11] Group 1: Partnership and Collaboration - The collaboration between Cadence and TSMC spans various technologies, including AI-driven electronic design automation (EDA), 3D integrated circuits (3D-ICs), and photonics, aimed at developing the world's most advanced semiconductors [2][4] - Cadence's AI design flows are now compatible with TSMC's advanced process technologies, including N3, N2, and A16, as well as new features in TSMC's 3DFabric [4][7] Group 2: Technological Innovations - Cadence's solutions include a range of tools such as the Innovus Implementation System, Quantus Extraction Solution, and Tempus Timing Solution, which support advanced process nodes [4][10] - New AI-driven features have been validated by TSMC, including automated design rule check (DRC) violation fixing, which enhances design efficiency for AI chip development [8][9] Group 3: Advanced IP Solutions - Cadence is delivering cutting-edge IP solutions on TSMC's N3P process technology, including the first HBM4 IP and high-speed memory interfaces like LPDDR6/5X [10] - The company is also leading in connectivity solutions with PCI Express (PCIe) 7.0 IP, achieving a data rate of 128GT/s, which supports emerging AI applications [10] Group 4: Market Impact - The partnership aims to empower customers by streamlining the journey from design to silicon, enhancing design performance and energy efficiency in AI systems [11][5] - Cadence's advancements are positioned to address the increasing demands of AI infrastructure, particularly in memory and interconnect bandwidth for next-generation AI workloads [10]