采用创新架构 新型“智能”芯片可大幅节能提速

Core Insights - A new "smart" chip developed by a collaborative research team, including the Politecnico di Milano, significantly reduces energy consumption while enhancing data processing speed, addressing long-standing computational energy bottlenecks [1][2] - The chip is based on a memory computing architecture, which minimizes data movement between memory and processor, leading to higher energy efficiency and faster processing speeds [1][2] Technology and Design - The chip features an integrated analog accelerator manufactured using standard CMOS technology, capable of solving both linear and nonlinear equations [1] - It includes two 64×64 programmable resistive memory arrays arranged in a grid format, utilizing static random-access memory technology combined with integrated resistors for multi-level programmability [1] Performance and Applications - The design allows complex computational tasks to be performed directly within the storage structure, eliminating the need to transfer data to external processors, thus significantly reducing computation latency [2] - Testing indicates that the chip achieves lower power consumption, shorter computation times, and a smaller chip area while maintaining accuracy comparable to traditional digital systems [2] Industry Collaboration - The project exemplifies international collaboration between academia and industry, with participation from universities and research teams across multiple countries, aiming to advance analog memory computing for high-performance and energy-efficient applications [2]