Xin Lang Cai Jing·2026-02-12 01:24Core Insights - Intel's next-generation Nova Lake processors are set to utilize TSMC's N2 process technology, featuring a base configuration of 8 P-cores and 16 E-cores, with a die size significantly larger than AMD's competitors [1][6] - The standard Nova Lake chip's die size is approximately 55% larger than AMD's Zen 5 CCD and about 44% larger than Zen 6 CCD [1][6] Processor Configuration - Both desktop and mobile versions of Nova Lake will adopt the 8P+16E base configuration, with options for entry-level and mainstream markets featuring 4P+8E configurations by disabling some cores [2][7] - Nova Lake will incorporate P-cores based on the Coyote Cove architecture and E-cores based on the Arctic Wolf architecture, with each cluster of P-cores containing 4MB of L2 cache [2][8] Dual Chip Design - Intel plans to introduce a flagship model with dual compute chips totaling 52 cores, with a standard dual-chip version's die size around 220mm² and a bLLC large cache version nearing 300mm², offering up to 288MB of L3 cache and a total cache size of 320MB [3][8] - The thermal design power (TDP) for these models will increase to 175W [3][8] Packaging and Compatibility - Despite the increased die size, all SKUs will utilize the same packaging and LGA1954 socket [3][9] - The bLLC technology differs from AMD's X3D stacking technology, and while Intel has similar additional cache technologies, they are not applied in Nova Lake [5][9]