M31完成4纳米MIPI M-PHY v5.0硅验证，加速布局UFS 4.1高速存储与车载市场

Core Insights - M31 Technology has successfully completed silicon validation of its MIPI M-PHY v5.0 IP on a 4nm process and is advancing research on the 3nm process, indicating its capability to support UFS 4.1 technology [1][2] Group 1: Product Development - The MIPI M-PHY v5.0 IP achieves a maximum single-channel transmission rate of 23.32 Gbps in HS-G5 mode, doubling the performance of the previous HS-G4 generation [2] - The IP incorporates Adaptive EQ technology and supports multi-level signal transmission, maintaining excellent signal integrity and low bit error rate under high-speed conditions [2] - An optimized hibernate design in the MIPI M-PHY v5.0 IP effectively reduces system power consumption, balancing high performance with low power usage [2] Group 2: Ecosystem and Solutions - M31 has built a comprehensive UFS solution ecosystem, integrating PHY IP, JEDEC-compliant UFSHCI v4.1 controller IP, and UniPro control layer IP to simplify system integration [3] - The platform includes ISO 26262 functional safety design processes and certifications, meeting stringent safety and reliability requirements for automotive and high-reliability applications [3] - M31 aims to be a trusted technology partner in building next-generation high-speed storage platforms, leveraging its long-term R&D strength in high-speed interface IP [3]