Synopsys Achieves Certification of its AI-driven Digital and Analog Flows and IP on Samsung Advanced SF2 GAA Process

Core Insights - Synopsys has achieved certification for its AI-driven digital and analog design flows on Samsung Foundry's SF2 process, validated through multiple test chip tapeouts [1][2][3] - The collaboration between Synopsys and Samsung focuses on enhancing power, performance, and area (PPA) for advanced semiconductor designs, with significant improvements reported [3][5] - Synopsys' AI-driven design technology has resulted in a 12% increase in performance, a 25% reduction in power consumption, and a 5% decrease in area compared to base designs [3] Design Flows and IP - The certified design flows utilize Synopsys.ai™ full-stack EDA suite, which enhances productivity and accelerates analog design migration for Samsung's Gate-All-Around (GAA) process technologies [1][3] - Synopsys has expanded its collaboration with Samsung to include new analog design migration reference flows, facilitating the transition from FinFET to GAA processes [6][11] Multi-Die and Heterogeneous Integration - Synopsys 3DIC Compiler supports the development of multi-die designs, qualified for Samsung Foundry's SF2 process, enabling advanced packaging and heterogeneous integration [8][11] - The collaboration aims to assist customers in transitioning to 2.5D and 3D advanced packaging designs, leveraging Synopsys' expertise in design and integration [8][11] New Design Techniques - Innovative design techniques such as backside routing and nanosheet cell design are being implemented to improve transistor performance efficiency and density [5][10] - These methodologies are expected to help customers meet their design goals more effectively, particularly in the context of Samsung's advanced process technologies [10][11]