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海力士,抢攻混合键合
半导体芯闻·2025-04-02 10:50

Core Viewpoint - SK Hynix emphasizes that the commercialization of the next generation of High Bandwidth Memory (HBM) requires technological advancements across various fields, particularly in power efficiency, and closer collaboration with major foundries [1][2]. Group 1: Development Focus - The three main tasks for the development of the next generation HBM are bandwidth, power, and capacity [1]. - Bandwidth is a critical measure of data transfer speed, with the next generation HBM4 expected to double the I/O ports to 2,048 compared to HBM3E [1]. - Customers are demanding even higher bandwidth, with some discussions mentioning up to 4,000 I/O ports, necessitating careful design considerations [1]. Group 2: Power and Capacity Improvements - Power consumption is closely related to logic processes, with HBM now requiring logic chips for controlling the stacked DRAM core chips [1][2]. - The capacity of HBM is directly linked to the number of DRAM stacks, with current commercial HBM supporting up to 12 layers, and future expansions expected to reach 16 to 20 layers [2]. - To achieve more layers within the height limit of 775 micrometers, the spacing between each DRAM must be reduced significantly [2]. Group 3: Technological Challenges - SK Hynix is advancing hybrid bonding technology, which connects DRAMs without using bumps, thereby reducing chip thickness and improving power efficiency [2]. - However, the commercialization of hybrid bonding faces challenges due to high technical difficulty and the need for reliable mass production [2]. - The company identifies cost reduction in manufacturing as a crucial task for the next generation HBM market [2].