DRAM图案化，新选择

Core Viewpoint - The article discusses the challenges and solutions in achieving spacing uniformity in DRAM chip metal layouts through techniques like stitched multi-patterning, emphasizing the effectiveness of double and triple patterning methods for different minimum pitch requirements [3][7][10]. Group 1: DRAM Chip Layout Challenges - DRAM chips have densely packed memory array features, but irregularities occur outside the array, leading to challenges in spacing uniformity [3][7]. - The spacing between features can vary significantly, with local maximum/minimum spacing ratios ranging from approximately 1.4 to 2 [3]. Group 2: Multi-Patterning Techniques - Stitched double patterning can achieve spacing uniformity by dividing layouts into alternating color stripes, allowing for effective exposure management [3][4]. - For minimum pitches above 40 nm, double patterning is deemed sufficient, while triple patterning is recommended for pitches below this threshold [6][8]. - Triple patterning can replace quadruple patterning for minimum pitches below 40 nm, demonstrating its efficiency [7][8]. Group 3: Long-Term Practices - Stitched double patterning has been the standard method for DRAM peripheral metal patterning and is expected to remain in use even at the 15 nm DRAM node [10].