Challenges with Current NoC Solution - Current NoC IP requires all instances to be placed on a block design canvas, making the block design a bottleneck for teams modifying NoC connectivity or attributes [4][6] - Routing AXI busses through the RTL hierarchy is a tedious process [5][6] - Additional complications arise when considering DFX use cases [6] Modular NoC Solution Overview - The modular NoC solution allows the NoC to be distributed among various design sources and hierarchies, resolving issues with the current solution [7] - The solution comprises three main steps: connecting AXI busses to Xilinx Parameterizable Macros (XPMs), adding constraint files (XDCs) to define connectivity and QoS parameters, and executing the `validate_noc` command [7][9][10] - The `validate_noc` command ensures full connectivity between XPM instances, runs DRCs, and executes the NoC compiler to generate the NoC solution [10][21] Key Features and Benefits - Teams can develop solutions independently, and the tool ensures the NoC is not overcommitted [8][10] - The solution maintains compatibility with the current solution, and simulation, debug flows, Vitis Unified IDE, and system software support are unchanged [11] - The solution is designed with enough flexibility to accommodate future enhancements such as security and isolation features [12] Supported Use Cases - AXI Master in the RTL accessing a port of the DDR memory controller on the block design [25] - A master on the BD accessing a peripheral in the RTL [26] - An RTL master accessing peripherals of the processing subsystem [26] - RTL to RTL NoC transfers [27] Tutorials and Further Learning - A series of tutorials are available for download, covering foundational concepts, DFX basics, advanced NoC properties, advanced DFX topics, and HBM [30]