半导体_AI 芯片测试-先进封装时代背后的隐形基础设施_MPI 相关举措：买入评级，风险较高-Semiconductors AI Chip Testing - The Hidden Infrastructure Behind the Age of Advanced Packaging Initiate on MPI at BuyHigh Risk

Summary of Conference Call Notes Industry Overview - The semiconductor industry is undergoing significant transformation driven by the rise of AI, which has increased the complexity of chip design and testing processes. Advanced packaging techniques such as CoWoS, InFo, and SoIC are now critical for AI computing systems, enabling the integration of multiple dies into a single package to enhance performance and bandwidth [10][84]. Key Companies Discussed Taiwan Semiconductor Manufacturing Company (TSMC) - TSMC's CoWoS capacity is projected to reach 1.2-1.3 million wafers in 2026 and 1.8-2 million in 2027, indicating strong demand for advanced packaging solutions [1]. ASE Technology Holding (ASEH) - ASEH is expected to see advanced packaging revenue reach US$4 billion by 2027, benefiting from TSMC's wafer testing business for AI chips. The company is focusing on both assembly and wafer testing, which positions it well for growth [2][9]. King Yuan Electronics Co. (KYEC) - KYEC is directly exposed to advanced testing requirements, particularly in the final test and validation of high-performance AI packages. Revenue growth is anticipated at 36% and 53% for 2026 and 2027, respectively, with a gradual expansion of gross margins [2][9]. MPI Corporation - MPI is positioned as a unique player in the probe card industry, with a strong sales CAGR of 48% projected from 2025 to 2027. The company is transitioning from a cyclical supplier to a structural beneficiary of AI-driven test complexity [3][4]. Core Insights and Arguments - Advanced packaging is reshaping the semiconductor value chain, making it a core architectural decision rather than a backend consideration. This shift is crucial for managing power and thermal constraints in AI chips [1]. - The complexity of AI chip designs necessitates longer testing processes, which increases the importance of probe cards in ensuring known-good-die (KGD) at the wafer level [10][23]. - The probe card market is characterized by high switching costs and strong vendor lock-in, as each chip requires a custom probe card, leading to sticky relationships between suppliers and customers [42][43]. Financial Projections - ASEH's target price has been raised to NT$340, reflecting a 9% and 32% increase in earnings projections for 2026 and 2027, respectively [9]. - KYEC's target price is now NT$330, with expectations of expanding gross margins due to robust AI chip shipment trends [9]. - MPI's target price is set at NT$2,800, with anticipated earnings growth of 77% and 64% for 2026 and 2027, driven by a better product mix and increased demand for MEMS probe cards [4]. Additional Important Points - The integration of advanced testing technologies, such as optical interferometry and 3D scanning, is essential for maintaining the structural integrity of AI chips during the testing process [18][19]. - The competitive landscape in the probe card market is dominated by FormFactor, Technoprobe, and MPI, with each company holding unique strengths in technology and market positioning [47][64][70]. - The trend towards chiplet designs in AI chips, as seen with Nvidia and Google, is expected to drive further demand for advanced packaging and testing solutions [11][84]. This summary encapsulates the critical insights and projections from the conference call, highlighting the evolving landscape of the semiconductor industry and the strategic positions of key players.