Core Insights - Arteris, Inc. has been selected by Esperanto Technologies for its CSRCompiler software, which enhances automation efficiency and reduces errors in the design process for system-on-chip (SoC) development [1][3] - Esperanto Technologies is focused on creating energy-efficient solutions for AI inference and high-performance computing (HPC) workloads, utilizing its ET-SoC-1 "supercomputer-on-a-chip" that integrates over 1,000 RISC-V cores [2][5] - The collaboration aims to address the growing demands of data centers and enterprise-edge markets by improving silicon performance and power efficiency [3] Company Overview - Arteris specializes in system IP for accelerating SoC development, providing network-on-chip (NoC) interconnect IP and integration automation technology to enhance product performance while reducing power consumption [4] - Esperanto Technologies develops high-performance computing solutions based on the RISC-V instruction set architecture, focusing on flexibility, scalability, and energy efficiency for demanding AI and non-AI applications [5]

SANTA CLARA, CA , May 22, 2024 (GLOBE NEWSWIRE) -- Highlights: Andes Technology and Arteris partnership aims to support the growing adoption of RISC-V SoCs by mutual customers. Focus is on high-performance/low-power RISC-V-based designs across a wide range of markets, including consumer electronics, communications, industrial applications and AI. The collaboration showcases integrated and optimized solutions with leading Andes RISC-V processor IPs and Arteris interconnect IP in silicon. CAMPBELL, Calif. – M ...

Core Insights - The partnership between Andes Technology and Arteris aims to enhance the adoption of RISC-V SoCs for various applications including AI, 5G, and consumer electronics [1][2] - The collaboration focuses on providing integrated solutions that combine Andes' RISC-V processor IPs with Arteris' interconnect IP, facilitating high-performance and low-power designs [1][3] Company Overview - Arteris is a leading provider of system IP that accelerates SoC development, offering technologies that improve performance, reduce power consumption, and shorten time to market [5] - Andes Technology is a founding member of RISC-V International, specializing in high-performance and low-power 32/64-bit embedded processor IP solutions, with a cumulative volume of over 14 billion Andes-Embedded SoCs by the end of 2023 [6][7] Product Details - The Andes QiLai RISC-V platform features a SoC with Andes' 64-bit AX45MP multiprocessor and NX27V vector processor, utilizing Arteris' FlexNoC interconnect IP for on-chip connectivity [2] - The platform supports various subsystems including PCIe, DDR, and SRAM, and is compatible with OpenSUSE Linux and Andes' software tools [2] Technology Benefits - Arteris' NoC IP provides scalable, low-latency, and power-efficient communication for complex SoC designs, enhancing the integration of high-performance CPU IPs [3] - The collaboration aims to accelerate the RISC-V ecosystem's growth by enabling rapid development and assessment of RISC-V software [3]

Arteris, Inc. (NASDAQ:AIP) Q1 2024 Earnings Conference Call May 2, 2024 4:30 PM ET Company Participants Erica Mannion - Sapphire IR Karel Janac - CEO Nicholas Hawkins - CFO Conference Call Participants Matt Ramsay - TD Cowen Hans Mosesmann - Rosenblatt Kevin Garrigan - WestPark Capital Gus Richard - Northland Operator Good afternoon, everyone, and welcome to the Arteris First Quarter 2024 Earnings Call. Please note, this call is being recorded and simultaneously webcast. All material contained in the webcas ...

Table of Contents UNITED STATES SECURITIES AND EXCHANGE COMMISSION Washington, D.C. 20549 FORM 10-Q (Mark One) x QUARTERLY REPORT PURSUANT TO SECTION 13 OR 15(d) OF THE SECURITIES EXCHANGE ACT OF 1934 For the quarterly period ended March 31, 2024 OR o TRANSITION REPORT PURSUANT TO SECTION 13 OR 15(d) OF THE SECURITIES EXCHANGE ACT OF 1934 For the transition period from to Commission file number 001-40960 Arteris, Inc. (Exact name of registrant as specified in its charter) (State or other jurisdiction of inc ...

Non-GAAP gross profit, Non-GAAP gross margin, Non-GAAP operating loss, Non-GAAP operating loss margin, Non-GAAP net loss, Non-GAAP net loss per share, free cash flow and free cash flow margin are Non-GAAP financial measures. Additional information on Arteris' historic reported results, including a reconciliation of these Non-GAAP financial measures to their most comparable GAAP measures, is included in the financial tables below. Second Quarter and Full Year 2024 Guidance: | | Q2 2024 | FY 2024 | | --- | -- ...

CAMPBELL, Calif., April 09, 2024 (GLOBE NEWSWIRE) -- Arteris, Inc. (NASDAQ:AIP), a leading provider of system IP which accelerates system-on-chip (SoC) creation, today announced that Rebellions, a pioneering AI semiconductor startup, will deploy FlexNoC interconnect IP plus Magillem Connectivity and Magillem Registers for its next-generation AI Hardware Accelerator Neural Processing Unit. The combination of Rebellions AI technology with Arteris' system IP will provide maximum flexibility and energy efficien ...

Arteris (AIP) is driving automotive electronics innovation forward with its recent announcement of expanded solutions tailored for the Armv9 architecture.In a strategic collaboration with Arm, Arteris aims to accelerate the development of cutting-edge automotive technologies, leveraging the latest Arm Automotive Enhanced technologies. This partnership underscores a pivotal moment in the automotive industry, signaling a shift towards more advanced product development and deployment methodologies.The integrat ...

Highlights: Arteris delivers on previously announced collaboration with Arm to speed up automotive electronics innovation with an emulation-based validation system for Armv9 and CHI-E based designs.Arteris aligned roadmap with Arm to enable designers to get to market faster with an optimized and pre-validated high-bandwidth, low-latency Ncore cache coherent interconnect IP for Arm's Automotive Enhanced (AE) compute portfolio.Collaboration integrates Arm processors with Arteris interconnect IP to enable auto ...

Highlights: -  Productive: Designed for maximum engineering productivity and time-to-market acceleration for connecting semiconductor IP blocks and sub-systems for Arm and RISC-V-based designs, accelerating time to results.-  Configurable: Scales across a mix of fully coherent, IO-coherent, non-coherent, memory and peripheral interfaces using a variety of NoC topologies, delivering best-in-class architectural flexibility.-  Functionally Safe: Ready to meet ISO 26262 requirements from ASIL B to ASIL D for au ...