TSMC(US:TSM) Jing Ji Ri Bao·2025-06-17 22:59Group 1 - The fan-out panel-level packaging is regarded as the next generation of advanced packaging, with major players like TSMC, ASE, and Powertech actively competing for opportunities in high-performance computing chip integration [1] - TSMC's technology, named CoPoS (Chip-on-Panel-on-Substrate), is expected to establish a pilot line in Chiayi by 2026, focusing on AI and HPC applications [2][1] - ASE has already established a production line for 300x300mm panel-level packaging in Kaohsiung, utilizing Fan-Out technology [3] - Powertech has been developing its fan-out panel-level packaging technology, named PiFO, since 2019, which is similar to TSMC's CoPoS [4][1] Group 2 - The advantages of panel-level fan-out packaging include larger substrate areas and heterogeneous integration capabilities, enhancing chip performance and functionality, making it suitable for 5G communication and IoT devices [1] - TSMC's CoPoS technology is a square design that allows for increased chip output, with mass production expected by 2028 [2] - TSMC also plans to launch a new CoWoS technology in 2027, which will integrate more logic and memory chips into a single package, aligning with the trends of CoPoS development [2]