徐易难：SVM——基于硬件的高效RISC-V处理器验证方法

Core Insights - The fifth RISC-V China Summit will be held from July 16 to 19, 2025, in Shanghai, featuring a main forum, multiple sub-forums, workshops, and a technology exhibition area of 4,500 square meters, attracting hundreds of companies and research institutions [1] - Processor verification is a critical yet challenging aspect of chip development, with over 86% of chip projects failing on the first tape-out and 75% exceeding their timelines, highlighting the urgent need for more efficient verification methods [3] Group 1: Processor Verification Challenges - The complexity of chip design has made processor verification a bottleneck in chip development, with a growing ratio of verification engineers to design engineers since 2007 [3] - Current verification methods, primarily co-simulation, struggle with the rapid expansion of the RISC-V instruction set, leading to increased verification workload and difficulties [3] - Simulation speed significantly decreases as processor scale increases, with a 92% drop in speed when moving from single-core to multi-core processors, presenting a major challenge for current verification methods [3] Group 2: SVM Method Introduction - A new verification method called SVM (Synthesis Verification Method) is proposed, which implements verification logic entirely in hardware, eliminating the performance overhead associated with data communication [5] - SVM faces three main challenges: efficient migration of existing software reference models to hardware, improving execution efficiency of hardware reference models, and addressing debugging and traceability issues in hardware environments [5][6] Group 3: SVM Technical Solutions - SVM employs several technologies, including semantic code migration to automate the transfer of instruction set semantics to hardware, and simplified hardware reference models to enhance verification efficiency [6] - A hardware debugging mechanism is integrated into SVM, providing tools such as hardware assertions and error logs to improve system debuggability [6] - Experimental results show that SVM achieved a verification speed of 60MHz on FPGA platforms, approximately 10 times faster than DiffTest, and 1.9MHz on Cadence Palladium, nearing ideal verification speeds [6] Group 4: Broader Implications - The research not only offers new insights for RISC-V processor verification but also provides valuable experiences applicable to hardware verification in other fields, indicating a promising future for processor verification technology [7]