台积电2nm产能告急：苹果包揽首批，AMD谷歌排队，英伟达已瞄准1.6nm

Core Insights - TSMC's advanced process capacity competition has officially begun, with global tech giants accelerating their entry into the 2nm process node, which is fully booked, highlighting the ongoing pressure on the semiconductor supply chain due to the combined demand for AI and mobile chips [1][2] - Nvidia's CEO Jensen Huang emphasized the urgent need for TSMC to operate at full capacity, confirming the industry's concerns about the tight supply of 2nm capacity [1] - Apple has secured over half of the initial 2nm capacity, with Qualcomm also being a major customer for 2026, while AMD plans to start 2nm CPU production in 2026 [1][2] Group 1: Capacity and Demand - The 2nm and 3nm process nodes at TSMC are facing capacity constraints, with high-performance computing and mobile chips competing for limited supply [2] - The 2nm family is expected to become a long-lifecycle node, with initial capacity ramp-up potentially exceeding that of the 3nm generation [2] - TSMC's CoWoS monthly capacity is projected to grow over 70% year-on-year by 2026, but this growth may still fall short of market demand [4] Group 2: Technological Developments - Nvidia plans to skip the 2nm process and move directly to the 1.6nm node, focusing on the A16 process, which features backside power delivery technology [3] - The A16 process is designed for high-performance computing products, improving signal integrity and power transmission efficiency, which is critical for large AI accelerators [3] - TSMC is upgrading its advanced packaging ecosystem to meet the demands of AI chips, which are increasingly adopting chiplet architectures and larger package sizes [4] Group 3: Challenges in Advanced Packaging - The supply-demand imbalance is a significant bottleneck, with challenges in improving the yield of large-scale system-level packaging [4] - As the packaging size of AI chips continues to grow, maintaining high yield rates has become increasingly difficult, potentially further constraining the supply capacity of advanced chips [4]