海力士+闪迪，存储芯片巨头力推 HBF 标准化

Core Viewpoint - The emergence of High Bandwidth Flash (HBF) technology is accelerating commercialization, aiming to fill the storage gap in AI inference, while existing technologies like HBM continue to evolve [1][2]. Group 1: HBF Technology Overview - HBF is not a new concept but is derived from the transition in the AI industry from training to large-scale inference, addressing the storage bottleneck in current architectures [2]. - HBF aims to provide a solution that combines high bandwidth, large capacity, and cost-effectiveness, bridging the gap between HBM's limited capacity and SSD's slower read/write speeds [2][3]. - HBF utilizes a restructured architecture and packaging optimization, incorporating 3D stacking technology from HBM and replacing storage media with NAND flash, achieving high-speed data transfer while retaining NAND's advantages [3]. Group 2: HBF and HBM Collaboration - HBF is designed to complement HBM rather than replace it, with HBM handling latency-sensitive tasks and HBF focusing on large-capacity sequential reads [4]. - The "H3 hybrid architecture" by SK Hynix demonstrates the synergy between HBM and HBF, showing significant performance improvements in various scenarios [4]. Group 3: Industry Response and Future Outlook - Major storage companies, including SK Hynix and SanDisk, are actively investing in HBF, with SanDisk being the pioneer in its commercialization [6]. - The establishment of a dedicated working group under the Open Compute Project (OCP) will facilitate the standardization of HBF technology, paving the way for its widespread adoption [6]. - HBF products are expected to be showcased by late 2026, with market demand projected to grow rapidly by 2030, driven by the expansion of AI inference applications [6]. Group 4: Challenges Ahead - Despite its promising outlook, HBF still faces inherent limitations related to NAND flash's slower write speeds, which could impact user experience in dynamic caching scenarios [7]. - Industry collaboration is necessary to address compatibility with existing GPU architectures, packaging complexity, and thermal management issues [7].