电子行业点评：台积电推进大芯片技术，芯片级玻璃基板有望受益

Investment Rating - The industry investment rating is "Leading the Market" [5] Core Viewpoints - TSMC is advancing its large chip packaging technology, with expectations to achieve certification for its CoWoS technology by 2027, which will support up to nine reticle sizes and twelve HBM4 memory stacks [2][3] - The demand for large substrates is increasing due to the requirements of large chip packaging, which poses challenges in system design and data center support, particularly regarding power and cooling [3] - Glass substrates are expected to benefit from the trend towards larger chips due to their advantages in flatness, thermal stability, and packaging size, which can reduce waste during chip production [4] Summary by Sections Investment Highlights - TSMC's CoWoS technology has evolved from N16 process in 2016 to the anticipated A16 process by 2027, driven by new demands such as AI [3] - The need for larger substrates, exceeding 120120 mm for the largest chips, will impact system design and data center configurations [3] Glass Substrate Advantages - Glass substrates offer superior electrical performance, efficiency, lower costs, and better thermal expansion coefficients compared to organic substrates, making them increasingly attractive in the industry [4] - The area of a 12-inch wafer is approximately 73,000 square millimeters, while a panel size of 510515 mm is about 263,000 square millimeters, allowing for more chips to be processed simultaneously [4] Investment Recommendations - The report maintains a "Leading the Market" rating, suggesting that the industry will continue to see growth driven by innovations in chip technology and domestic demand for alternatives [4]