电子行业深度报告：AI基建，光板铜电：光、铜篇：主流算力芯片 Scale up&out 方案全解析

Investment Rating - The industry investment rating is maintained at "Overweight" [1] Core Insights - The report emphasizes that 2026 will be a critical year for the commercial release of GPUs and the large-scale deployment of CSP ASICs, leading to a surge in demand for interconnect solutions in data centers. Copper cables are highlighted as the optimal solution for short-distance, low-cost interconnects, while the demand for optical modules is expected to rise significantly due to the increasing GPU deployment [5][54]. Summary by Sections 1. Nvidia - The report details the upgrades in high-bandwidth, low-latency interconnects for Nvidia's Rubin, with a focus on the sixth-generation NVLink and the configuration of NVSwitch chips to achieve a symmetrical bandwidth of 129.6TB/s [10][12]. - The optical module demand ratio for the Rubin NVL144 configuration is projected to reach 1:12 under full CPX configuration, indicating a significant increase in the need for optical components as server clusters expand [16][18]. 2. Google - Google's TPU architecture is discussed, highlighting the use of a 3D Torus topology for high-bandwidth interconnects, with each TPU chip providing a bandwidth of 4.8TB/s [20][23]. - The report outlines the multi-layer network structure supporting the TPU scale-out, which includes 9216 TPU chips and utilizes a combination of TOR and Leaf/Spine switches to manage traffic efficiently [29][30]. 3. Amazon - Amazon's Trainium3 network architecture is characterized by high-density interconnects and flexible scaling capabilities, utilizing PCIe 6.0 technology for efficient communication between chips [32][33]. - The dual-network division (ENA for north-south traffic and EFA for east-west traffic) is designed to support the scaling of AI cluster communications, enhancing overall network performance [35][36]. 4. Meta - Meta's Minerva cabinet is designed for high-speed interconnects, achieving a symmetrical bandwidth of 204.8Tbps through the integration of Tomahawk5 switches and copper backplane technology [37][39]. - The DSF (Disaggregated Scheduled Fabric) network architecture is introduced to address bandwidth bottlenecks and congestion in large-scale AI training environments, featuring a layered design for improved resource utilization [43][48]. 5. Investment Recommendations - The report suggests focusing on the core sectors of optical and copper interconnects, as both are expected to experience significant growth driven by the increasing demand for data center interconnect solutions [54].