Reducing Clock Skew in AMD Versal™ Devices

Versal Clocking Architecture Enhancements - AMD Versal devices feature a segmented clocking structure, utilizing global clocking with regional or global load placement for efficient resource utilization and improved clock characteristics [4][5] - Versal architecture introduces BUFG Fabric for high-fanout routing with predictable delay and MBUFG for fast division of global clocks, reducing skew between synchronous clock domains [6][7] - Clock trees are more flexible for targeted skew reduction in multi-SLR devices, with calibrate deskew tuning clock distribution at startup [7][8] Clock Routing and Deskew Schemes - Versal employs a Vertical H-tree to minimize clock skew in both vertical and horizontal directions [12] - Basic deskew minimizes insertion delay, suitable for I/O interfaces and synchronous CDC paths with parallel BUFG [18] - Calibrated deskew, used in Versal SSIT devices, balances programmable delays during startup to minimize skew across the clock network [19][32] Calibrated Deskew Considerations - Calibrated deskew is off by default and should be enabled based on timing report analysis, particularly for large skew issues and maximizing SLR crossing performance [39][40] - Calibrated deskew is more beneficial in larger Versal SSIT devices with higher performance clocks (over 350 MHz) and numerous clock loads spanning all SLRs [42] - Avoid using calibrated deskew if synchronous CDC clocks employ parallel clock buffers, BUFG_FABRIC drives high fanout control signals, I/O interface clocks are used, or the clock root is in the GT column or VNOC columns [43]