1.4nm，巅峰之争

Core Viewpoint - The article discusses the competitive landscape in semiconductor manufacturing, focusing on advancements by TSMC and Intel in their respective processes and technologies, particularly in the context of the A14 process node and High NA EUV lithography. TSMC Developments - TSMC is transitioning from FinFET to Nanosheet technology, with a focus on CFET (Complementary FET) devices for further miniaturization and power reduction [1][3] - TSMC showcased its first CFET transistor with a gate pitch of 48nm at the 2023 IEDM, marking a significant milestone in CFET technology [3] - The company is also exploring new interconnect technologies to enhance performance, including new via schemes and materials like graphene to reduce resistance and coupling capacitance [7] Intel Innovations - Intel's upcoming 14A process node, set for risk production in 2027, aims to reduce power consumption by up to 35% and improve performance per watt by 15% to 20% compared to the 18A node [8][9] - The introduction of Turbo Cell technology is designed to optimize critical paths in CPU and GPU designs, enhancing overall performance without compromising power efficiency [10][12] - Intel plans to utilize High NA EUV lithography for its 14A process, despite concerns over cost and complexity, while also maintaining a Low NA EUV alternative to mitigate risks [13][19] High NA EUV Strategy - TSMC has decided not to use High NA EUV for its A14 process due to cost concerns, opting for traditional 0.33 NA EUV technology instead [13][14] - Intel has installed a High NA EUV lithography machine and is committed to exploring its use in the 14A process, while ensuring compatibility with existing design rules to alleviate customer concerns [15][17] - The article highlights the ongoing debate over the cost-effectiveness of High NA EUV versus Low NA EUV, with Intel asserting that both processes can achieve similar yields [17][18]