探索2.5D/3D封装EDA平台协同创新模式

Core Viewpoint - The article discusses the advancements and challenges in the 2.5D/3D IC backend design EDA tools, emphasizing the need for collaborative innovation in the heterogeneous integration and advanced packaging sectors to meet the growing demands for AI computing power and overcome existing technological barriers [3][4][5]. Group 1: Event Overview - The "2025 TrendBank Heterogeneous Integration Packaging Industry Conference" was held on April 29, 2025, in Ningbo, co-hosted by TrendBank and Yongjiang Laboratory, with support from Zhuhai Silicon Core Technology Co., Ltd. and Ningbo Electronics Industry Association [1]. - Dr. Zhao Yi, founder and chief scientist of Zhuhai Silicon Core Technology Co., Ltd., delivered a keynote speech focusing on the EDA platform for 2.5D/3D advanced packaging, exploring collaborative innovation in backend design, simulation, and verification [1][3]. Group 2: Industry Insights - The demand for AI computing power has surged, outpacing the growth rate predicted by Moore's Law, leading to a conflict between increasing computational needs and the slow performance growth of chips [4]. - Advanced packaging technologies, such as stacked chips, allow for flexible integration and high-density interconnections, significantly enhancing integration levels and driving improvements in computing speed and storage capacity [4][5]. Group 3: Technical Challenges - The design complexity of stacked chips has increased exponentially, creating a scarcity of comprehensive EDA design toolchains that can address the new challenges in design, testing, and simulation [5]. - Key challenges in the 2.5D/3D Chiplet design field include achieving a cohesive top-level architecture, managing various packaging types, and understanding the benefits of architectural-level analysis [5]. Group 4: Solutions and Innovations - Zhuhai Silicon Core Technology has developed the 3Sheng Integration Platform, which provides a comprehensive solution covering the entire backend design process for Chiplets [5]. - The platform integrates five centers: architecture design, physical design, multi-die testing, analysis simulation, and multi-Chiplet integration verification, facilitating a collaborative design approach that maximizes performance, cost, and testability [5].