全流程EDA工具为 2.5D/3D 封装实现降本增效

Core Viewpoint - The article discusses the advancements and challenges in the field of Electronic Design Automation (EDA) for 2.5D/3D stacked chip design, emphasizing the need for innovative tools and methodologies to enhance design efficiency and address the complexities of multi-chip integration [2][5][9]. Group 1: EDA Tools and Innovations - EDA suppliers are exploring new methods to improve the efficiency of design and verification engineers, particularly in the context of advanced chips that require early-stage multi-physical field analysis [2]. - The 3Sheng Integration Platform developed by Silicon Chip Technology integrates system-level planning, physical realization, analysis, testability, and reliability design, supporting agile development and customizable collaborative design optimization for 3D heterogeneous integration systems [3][5]. - The introduction of the 3Sheng_Zenith system modeling tool aims to address key challenges in Chiplet and advanced packaging design, facilitating system-level planning, interconnect design, and early system analysis [9][10]. Group 2: System-Level Planning and Design - System-level planning involves partitioning a System on Chip (SoC) into smaller Chiplet modules, allowing for flexible layout planning and resource optimization [13][15]. - Chiplet modeling is a core step in system-level planning, ensuring design repeatability and scalability, with each Chiplet being treated as an independent IP for physical planning [16]. - The floorplan optimization ensures efficient resource allocation among Chiplets in 2.5D/3D integrated circuits, preparing for subsequent routing and simulation [19]. Group 3: Testing and Reliability - The design of multi-chip integrated systems requires careful planning for testability and fault tolerance, as the complexity of interconnects can pose risks to system stability and quality [19]. - The 3Sheng_Zenith tool incorporates early DFT (Design for Testability) and FT (Fault Tolerance) design resources to ensure the stability and integrity of 3D systems [19][21]. Group 4: Early System Analysis - Early system analysis involves multi-level co-design and simulation, utilizing various analysis tools to ensure the reliability and stability of the designed system [30][32]. - The robustness of interconnect routing is assessed to ensure performance, particularly in high-bandwidth, high-power scenarios, by checking parasitic parameters and overall routing constraints [33]. - Manufacturing cost assessments are integral to Chiplet architecture design, considering wafer, packaging, bonding, and testing design costs to ensure the feasibility of the new system [34][36].