国泰海通｜电子：3D DRAM：开启端侧AI蓝海

Core Viewpoint - The long-term proposition of DRAM is transitioning from 2D to 3D architecture, with NPU as a co-processor likely to be the next trend in edge technology when combined with 3D DRAM [1][2][4]. Industry Insights and Investment Recommendations - The integration of NPU as a co-processor with 3D DRAM is expected to be a significant trend in edge technology, leading to an "overweight" rating for the industry [2]. - Current advancements in DRAM technology face challenges as the process node has reached 10nm, making it increasingly difficult to achieve stable charge storage and read/write operations in smaller spaces [3]. - The hybrid bonding method improves stacking height limitations and is seen as the future technical path for 3D DRAM, allowing for more stacked layers and better thermal management compared to existing Micro bump technology [3]. AI Application and Memory Bandwidth - AI applications are diversifying rather than conforming to a unified model, with hardware developments paving the way for new technologies that support AI's ubiquitous and always-on capabilities [4]. - The primary bottleneck for AI edge inference speed is memory bandwidth rather than computational power, with 3D DRAM addressing memory limitations effectively [5]. - For instance, Qualcomm's Snapdragon 8 GEN 3 has a computational capability of approximately 45 TOPs and a memory bandwidth of about 67 GB/s, highlighting the significant impact of memory bandwidth on performance [5].