三维堆叠芯片DFT！系统级测试EDA：测试监控、诊断、自修复的本地化可测性互连方法

Core Viewpoint - The article emphasizes the significance of the 3Sheng Integration Platform developed by Silicon Chip Technology for the design and testing of 2.5D/3D stacked chips, highlighting its innovative features and capabilities in enhancing reliability and performance in chip systems [3][34]. Group 1: 3Sheng Integration Platform - The 3Sheng Integration Platform integrates system-level planning, physical implementation, analysis, testability, and reliability design for 3D stacked chips, supporting agile development and customizable collaborative design optimization [3][34]. - The platform features a unified data foundation and combines five engines: system, test, synthesis, simulation, and verification, showcasing originality in multiple functionalities and performance [3]. Group 2: Importance of DFT in Stacked Chips - Design for Testability (DFT) is crucial in stacked chip systems due to the unique interconnect testing requirements arising from multiple chiplets, necessitating specific testing before and after interconnection [6][10]. - The interconnect interfaces in stacked chips introduce new testing demands, including compatibility, connectivity integrity, and defect detection, which are not present in conventional chips [10][12]. Group 3: Testing Processes and DFT Requirements - The testing process for stacked chips includes pre-bond, mid-bond, post-bond, and final tests, with the accuracy and completeness of these tests being vital for product quality and cost-effectiveness [13][15]. - DFT plays a significant role in ensuring testability, controllability, and self-repair capabilities within the stacked chip systems, addressing various reliability concerns [15][16]. Group 4: Cross-Die Testing Solutions - The SiChip DFT technology offers a mixed testing solution that includes scan chains, boundary scan, built-in self-test (BIST), and diagnostic channels, adhering to various IEEE standards [17][19]. - The architecture design phase must consider DFT testing access mechanisms to ensure compatibility and universality across different manufacturers' dies [19][20]. Group 5: Diagnostic Testing and Functional Simulation - The 3Sheng Ocean EDA testing solution integrates fault diagnosis, functional simulation, and adaptive repair technologies, covering wafer-level circuit testing and final functional testing [25][27]. - The solution aims to optimize testing resources and reduce testing time while enhancing fault coverage, achieving a 50% reduction in testing costs and a 99.99% fault coverage rate [27]. Group 6: Fault Tolerance Design - The SiChip EDA DFT solution supports comprehensive redundancy and fault tolerance, utilizing eFPGA technology to create a full-process redundancy solution from top-level planning to physical implementation [29][31]. - The design allows for dynamic routing and protocol conversion, enhancing interconnect channel utilization and addressing thermal coupling and signal interference issues [31].