半导体行业观察·2025-06-12 00:41Core Viewpoint - The article discusses the significant advancements and challenges in TSMC's CoWoS (Chip-on-Wafer-on-Substrate) packaging technology, particularly in relation to NVIDIA's evolving needs in the AI sector, highlighting the shift towards CoWoS-L and the emergence of CoPoS (Chip-on-Panel-on-Substrate) as a potential alternative [1][3][10]. Group 1: TSMC and NVIDIA Collaboration - TSMC has become a crucial partner for NVIDIA, especially in the CoWoS domain, with NVIDIA's CEO Jensen Huang stating that they have no alternative to TSMC for this advanced packaging technology [1]. - NVIDIA is transitioning to use more CoWoS-L packaging for its latest Blackwell series products, which require high bandwidth interconnects between chips [3][5]. Group 2: CoWoS Technology Evolution - The CoWoS technology is facing challenges due to increasing chip sizes, with AI chips potentially reaching dimensions of 80x84 mm, limiting the number of chips per wafer [5]. - TSMC is exploring alternatives to traditional solder paste bonding methods due to difficulties in maintaining yield rates, including the development of no-solder paste bonding technology [6][9]. Group 3: Future Developments in Packaging - TSMC plans to introduce CoWoS-L with a mask size of 5.5 times the current size by 2026, and a record 9.5 times mask size CoWoS by 2027 [9]. - CoPoS technology is being developed as a next-generation packaging solution, with plans for mass production by 2029, aiming to enhance efficiency and reduce costs by utilizing larger rectangular substrates [12][14]. Group 4: Comparison of Packaging Technologies - CoPoS differs from FOPLP (Fan-out Panel-Level Packaging) in that it uses an interposer for better signal integrity and power delivery, making it suitable for high-performance applications [13]. - The transition from traditional organic substrates to glass substrates in CoPoS is expected to improve interconnect density and thermal stability, positioning it as a potential successor to CoWoS-L [14].