半导体芯闻·2025-06-12 10:04Core Viewpoint - The article discusses the significant rise of TSMC's CoWoS packaging technology, driven by the increasing demand for GPUs in the AI sector, particularly through its partnership with NVIDIA, which has deepened over time [1][3]. Group 1: CoWoS Technology and NVIDIA Partnership - NVIDIA has emphasized its reliance on TSMC for CoWoS technology, stating that it has no alternative partners in this area [1]. - TSMC has reportedly surpassed ASE Group to become the largest player in the global packaging market, benefiting from the growing demand for advanced packaging solutions [1]. - NVIDIA's upcoming Blackwell series will utilize more CoWoS-L packaging, indicating a shift in production focus from CoWoS-S to CoWoS-L to meet the high bandwidth requirements of its GPUs [3]. Group 2: Challenges and Innovations in CoWoS - The increasing size of AI chips poses challenges for CoWoS packaging, as larger chips reduce the number of chips that can fit on a 12-inch wafer [4]. - TSMC is facing difficulties with the use of flux in CoWoS, which is essential for chip bonding but becomes problematic as the size of the interposer increases [4][5]. - TSMC is exploring flux-free bonding technologies to improve yield rates and address the challenges posed by flux residue [5]. Group 3: Future Developments and Alternatives - TSMC plans to introduce CoWoS-L with a mask size of 5.5 times larger by 2026 and aims for a record 9.5 times larger version by 2027 [8]. - The company is also developing CoPoS technology, which replaces traditional wafers with panel substrates, allowing for higher chip density and efficiency [9][10]. - CoPoS is positioned as a potential alternative to CoWoS-L, targeting high-performance applications in AI and HPC systems [12]. Group 4: Technical Comparisons - FOPLP and CoPoS both utilize large panel substrates but differ in architecture; FOPLP does not use an interposer, while CoPoS does, enhancing signal integrity for high-performance chips [11]. - CoPoS is transitioning to glass substrates, which offer better performance characteristics compared to traditional organic substrates [12]. - The shift from round wafers to square panels in CoPoS aims to improve yield and reduce costs, making it more competitive in the AI and 5G markets [12]. Group 5: Challenges Ahead - Transitioning to square panel technology requires significant investment in materials and equipment, along with overcoming technical challenges related to pattern precision [14]. - The demand for finer RDL line widths poses additional challenges for suppliers, necessitating breakthroughs in RDL layout technology [14]. Conclusion - The future of TSMC's packaging technologies appears promising, with ongoing innovations and adaptations to meet the evolving demands of the semiconductor industry [14].