0.7nm芯片，路线图更新

Core Viewpoint - The article discusses the advancements in semiconductor technology, particularly focusing on the transition to 2nm technology nodes and the role of Gate-All-Around (GAA) nanosheet transistors in this evolution [1][2][30]. Group 1: GAA Nanosheet Technology - GAA nanosheet devices are positioned as successors to FinFET technology, allowing for further miniaturization of SRAM and logic standard cells [1]. - The GAA architecture features vertically stacked nanosheet channels, enhancing gate control over the channel even at shorter channel lengths [1][2]. - The transition to Complementary FET (CFET) technology is expected to occur after at least three generations of GAA nanosheet technology [2]. Group 2: Forksheet Device Architecture - Forksheet architecture was introduced by imec as a scaling booster for SRAM and logic standard cells, allowing for tighter n-to-p spacing and further area reduction [4][5]. - The inner wall forksheet design initially faced manufacturability challenges, particularly regarding the thin dielectric wall required for achieving a 90nm logic standard cell height [7]. - The outer wall forksheet design was developed to address these challenges, simplifying the manufacturing process while maintaining performance and area scaling advantages [9][11][30]. Group 3: Performance and Integration - The outer wall forksheet design allows for improved gate control and reduced parasitic capacitance compared to traditional nanosheet devices [15][16]. - The wall-last integration method enables effective source/drain stress sources, enhancing performance through full channel strain [21][22]. - A benchmark study indicated that the outer wall forksheet SRAM unit area is reduced by 22% compared to A14 nanosheet architecture, demonstrating significant area efficiency [26]. Group 4: Future Outlook - imec is exploring the compatibility of the outer wall forksheet design with CFET architecture, aiming to leverage the PPA benefits from this innovative scaling booster [30].