0.7nm芯片会用的晶体管

Core Viewpoint - Leading foundries and IDM manufacturers are advancing towards the production of 2nm (or equivalent) technology nodes, with GAA (Gate-All-Around) nanosheet transistors playing a crucial role in this transition [1][2]. Group 1: GAA Nanosheet Technology - GAA nanosheet devices are designed to further reduce the size of SRAM and logic standard cells by vertically stacking two or more nanosheet-like conductive channels [1]. - The configuration allows designers to minimize the height of logic standard cells while enhancing gate control over the channel, even at shorter channel lengths [1]. - GAA nanosheet technology is expected to last at least three generations before transitioning to CFET (Complementary FET) technology, with the A10 node anticipated to have a cell height as low as 90nm [2]. Group 2: Forksheet Device Architecture - Forksheet device architecture, introduced by imec, offers greater scalability compared to conventional GAA nanosheet technology [4][5]. - The inner wall forksheet structure allows for tighter n-to-p spacing, enabling further reduction in cell area while still providing performance improvements [5]. - imec demonstrated the manufacturability of the 300mm inner wall forksheet process flow, confirming its potential to extend the roadmap for logic and SRAM nanosheets to the A10 node [6]. Group 3: Challenges and Improvements - Despite successful hardware demonstrations, concerns regarding the manufacturability of the inner wall forksheet architecture led imec to reconsider its design [6][8]. - The outer wall forksheet design, presented at VLSI 2025, aims to reduce process complexity while maintaining performance and area scalability [9][11]. - The outer wall forksheet allows for a thicker dielectric wall (up to 15nm) without affecting the 90nm cell height, simplifying the integration process [11][16]. Group 4: Performance and Power Advantages - The outer wall forksheet is expected to provide significant advantages over the inner wall design in five key areas, including improved gate control and reduced parasitic capacitance [14][18]. - A benchmark study indicated that the area of SRAM cells based on the outer wall forksheet is reduced by 22% compared to A14 nanosheet architecture [25]. - The ability to achieve full channel strain in the outer wall forksheet design is anticipated to enhance performance, particularly in driving current [19][25]. Group 5: Future Outlook - imec is currently exploring the compatibility of the outer wall forksheet design with CFET architecture and the potential PPA benefits that could arise from this innovative scaling booster [27].