三维芯片堆叠, 革新下一代计算架构

Core Viewpoint - The article discusses the development of a new power technology for 3D integrated chips using a three-dimensional stacked computing architecture, addressing the demand for high-performance computing applications that require high memory bandwidth, low power consumption, and low power noise [3][6]. Group 1: Technology Development - Researchers have developed key technologies such as precision high-speed bonding and adhesive techniques to meet the needs of high-performance computing applications [3]. - The traditional system-in-package (SiP) methods are limited in size, necessitating the development of new chip integration technologies [3]. - The innovative 2.5D/3D chip integration method named BBCube was conceived by a research team from Science Tokyo [3][5]. Group 2: Research Achievements - The research team successfully bonded different sized chips onto a 300 mm wafer with a spacing of only 10 μm, achieving a bonding time of less than 10 milliseconds [5]. - Over 30,000 different sized chips were manufactured on the wafer without any chip detachment failures [5]. - A new adhesive material, DPAS300, was developed, exhibiting good adhesion and thermal stability for the COW and wafer-to-wafer processes [5]. Group 3: Performance Enhancements - To enhance memory bandwidth and power integrity of BBCube, a 3D xPU-on-DRAM architecture was adopted, incorporating new power distribution highways [6]. - Innovations reduced the energy required for data transmission to one-fifth to one-twentieth of that of traditional systems, while power noise was suppressed to below 50 mV [6]. - The chip integration technology developed by the researchers has the potential to transform the next generation of computing architectures [6].