半导体行业观察·2025-07-01 01:03Core Viewpoint - The next significant leap in semiconductor packaging will require a series of new technologies, processes, and materials that will collectively achieve an order-of-magnitude performance improvement, which is crucial for the AI era [1]. Group 1: Advances in Cooling Technologies - Liquid cooling technology at the chip level is emerging as forced air cooling reaches its limits, with up to 40% of power used for current delivery and heat dissipation [4]. - TSMC's silicon integrated micro-cooler (IMEC-Si) is being tested for reliability, designed to handle over 3,000 watts of uniform power dissipation under specific conditions [6]. - The demand for direct liquid cooling is increasing, with innovative concepts like using chips as coolants being proposed [7]. Group 2: Hybrid Bonding and Interconnects - Hybrid bonding with fine-pitch multilayer redistribution layers (RDL) is gaining attention as a cost-effective solution for high-speed interconnects [14]. - Intel's hybrid bonding can achieve spacing as small as 1µm, which is critical for advanced applications [5][17]. - The transition from traditional dielectric materials to polymer/copper hybrid bonding is being explored to enhance performance [16]. Group 3: Backside Power Delivery - Backside power delivery significantly reduces voltage drop related to transistor power supply, but it also exacerbates heat issues [19]. - IBM has developed an anisotropic model for precise heat transfer calculations in backend stacks, emphasizing the importance of thermal considerations in design [21]. - The implementation of backside power delivery is expected to lead to a 10% to 30% reduction in thermal losses [23]. Group 4: Co-Packaged Optical Devices - The demand for faster data networks is driving the integration of optical engines with GPUs and HBM in a single package, significantly increasing data transmission speeds [26]. - Co-packaged optical devices (CPO) are expected to achieve a 32-fold increase in bandwidth by bringing optical engines closer to processors [26]. - However, challenges remain regarding thermal management and warpage sensitivity in CPO implementations [28].