LPDDR6，正式发布

Core Viewpoint - The release of the new LPDDR6 standard by JEDEC represents a significant advancement in memory technology, aimed at enhancing speed, efficiency, and security for mobile devices and artificial intelligence applications [1][5]. Performance Enhancements - LPDDR6 features a dual-channel architecture that maintains a 32-byte access granularity while allowing flexible operations, optimizing channel performance with two sub-channels per chip, each having 12 data signal lines [3][4]. - The standard includes dynamic write non-target on-die termination (NT-ODT) to improve signal integrity based on workload demands [3]. Power Efficiency - LPDDR6 operates at a lower voltage and power consumption compared to LPDDR5, utilizing two VDD2 power supplies to meet increasing power efficiency demands [3]. - Additional energy-saving features include low-power dynamic voltage frequency scaling (DVFSL) and support for partial self-refresh and active refresh to reduce refresh power [4]. Security and Reliability - The standard incorporates features such as command/address (CA) parity checking, error clearing, and built-in self-test (MBIST) to enhance error detection and system reliability [5]. - The Carve-out Meta mode allocates specific memory areas for critical tasks, improving overall system reliability [4]. Industry Support and Impact - Industry leaders, including Qualcomm and MediaTek, express confidence that LPDDR6 will significantly impact mobile applications, edge AI computing, data centers, and automotive sectors [5][6][7]. - The standard is expected to meet the growing demands for AI inference, providing the necessary speed, bandwidth, and capacity while maintaining cost, efficiency, and reliability [5][8].