半导体芯闻·2025-07-16 10:44Core Viewpoint - Nomura indicates that TSMC's CoPoS packaging technology mass production timeline may be delayed from the original plan of 2027 to 2029-2030, potentially forcing NVIDIA to shift its chip design strategy for the Rubin Ultra GPU to an MCM architecture to avoid limitations of single-module packaging [2][3][4]. Group 1: TSMC's CoPoS Technology Delay - TSMC's CoPoS (chip-on-panel-on-substrate) technology aims to enhance area utilization through larger panel sizes (e.g., 310x310mm) to meet AI GPU demands [4]. - The delay in CoPoS mass production is attributed to technical challenges, particularly in managing panel and wafer discrepancies, warpage control, and additional redistribution layers (RDL) [4][5]. - The expected mass production timeline has shifted from 2027 to potentially late 2029 [4][5]. Group 2: Impact on NVIDIA's Product Strategy - The delay in CoPoS may compel NVIDIA to adopt an MCM architecture for the Rubin Ultra GPU, distributing four Rubin GPUs across two modules connected via a substrate [5][6]. - This adjustment is similar to Amazon's AWS Trainium 2 design, which utilizes CoWoS-R and MCM to integrate computing chips and HBM on a single substrate [6]. - While this change may help NVIDIA mitigate delays, it could also increase design complexity and costs [6]. Group 3: TSMC's Capital Expenditure Adjustments - TSMC's capital expenditure allocation may shift towards wafer-level multi-chip modules (WMCM) and system-on-chip (SoIC) technologies due to the CoPoS delay [7]. - Nomura maintains its forecast for TSMC's CoWoS capacity, expecting monthly wafer production to reach 70,000 and 90,000-100,000 by the end of 2025 and 2026, respectively [7]. - The report warns that market expectations for WMCM may be overly optimistic, while those for SoIC are more conservative [8].