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知合计算:打响高性能RISC-V突围战
半导体行业观察·2025-07-18 00:57

Core Viewpoint - The article discusses the evolution of chip architectures, highlighting the rise of RISC-V as a new engine for transformation in the global chip industry, particularly in the context of AI and IoT, due to its open-source, simplified, and cost-effective nature [1][2]. Group 1: RISC-V's Current Status and Challenges - Despite the growing interest in RISC-V for high-performance applications, there is a lack of benchmark products that can compete with ARM and x86 architectures [2][3]. - The first-tier RISC-V products, such as SiFive's P870-D and others, still lag behind mainstream ARM and x86 offerings in terms of performance [2][3]. - The absence of high-performance RISC-V chips may hinder the development of a robust software ecosystem, as developers are less inclined to invest in a less popular architecture [2][3]. Group 2: Key Developments and Innovations - Knowledge Computing has introduced the "Archimedes" series of CPUs, which aim to integrate general computing and AI inference capabilities efficiently [6][15]. - The new RISC-V CPU core is positioned among the top-tier high-performance CPUs, capable of matching the performance of leading ARM and x86 products [7][14]. - The CPU core supports a wide range of RISC-V extensions and is designed to provide a complete software stack, including tools and operating systems, to facilitate easier adoption [9][12]. Group 3: Market Strategy and Ecosystem Development - Knowledge Computing is focusing on specific application scenarios, such as edge servers and AI model inference, to drive the adoption of RISC-V and build a more robust ecosystem [21][22]. - The company aims to establish benchmark products that can attract more developers and partners to participate in the RISC-V ecosystem, thereby enhancing market confidence [28][26]. - The strategy emphasizes collaboration over competition among domestic manufacturers to strengthen RISC-V's position in the global market and enhance its standard-setting capabilities [34][35].