半导体行业观察·2025-07-20 04:06Core Viewpoint - Tsinghua University's research team has made significant advancements in wafer-scale chips, presenting three key research outcomes at the ISCA 2025 conference, focusing on high-performance AI model training and inference scenarios [1][9]. Group 1: Research Achievements - The team developed a collaborative design optimization methodology for wafer-scale chips, integrating computational architecture, integration architecture, and compilation mapping, which has gained recognition in both academia and industry [1][9]. - The research includes a paper on interconnect-centric computational architecture, addressing physical constraints and proposing a "Tick-Tock" co-design framework that optimizes physical and logical topologies [10][12][13]. - Another paper presents a vertically stacked integration architecture that addresses the challenges of tightly coupled heterogeneous design factors, achieving significant improvements in system-level integration density and performance metrics [14][18]. Group 2: Wafer-Scale Chip Technology - Wafer-scale chips represent a disruptive technology that integrates multiple computing, storage, and interconnect components into a single chip, significantly enhancing computational power and efficiency [3][8]. - The design allows for a larger number of transistors to be integrated, overcoming limitations faced by traditional chips, and achieving a chip area of approximately 40,000 square millimeters [4][8]. - The architecture enables higher interconnect density and shorter interconnect distances, resulting in performance and energy efficiency improvements, with potential density reaching over twice that of current supernode solutions [8][9]. Group 3: Industry Context - Major global tech companies, including Tesla and Cerebras Systems, are investing in wafer-scale chip technology, with Tesla's Dojo chip achieving 9 PFlops of computing power and Cerebras' WSE-3 chip integrating 400 trillion transistors [24][25]. - TSMC is also advancing wafer-scale systems, aiming for mass production by 2027, which will enhance computational density and data transfer efficiency [25]. - The advancements in wafer-scale chips are critical for the AI industry's future, as they provide a foundation for high-performance computing necessary for large-scale AI applications [23][26].