AI时代的RISC-V芯片：奕行智能的破局之道

Core Viewpoint - The development of AI is fundamentally changing the software programming paradigm, leading to the emergence of Software 3.0, where natural language prompts are replacing traditional programming code, and large language models (LLMs) are becoming the new programming interface [2][3]. Group 1: Software Evolution - Software 1.0 was characterized by human-written code, while Software 2.0 shifted to neural networks, requiring data preparation and parameter training [2]. - Software 3.0 represents a significant transformation in software development, driven by the rise of large language models [2]. - The transition to Software 3.0 necessitates advancements in hardware, referred to as Hardware 3.0, to support new computational demands [2][3]. Group 2: Hardware Requirements - The dominance of CPUs in Software 1.0 has shifted to GPUs in Software 2.0 due to the need for parallel processing capabilities [3]. - The rapid development of transformer-based models in Software 3.0 has led to the increased adoption of Domain-Specific Architectures (DSA) [5]. - A balance between specialized efficiency and programming generality is crucial for the development of Hardware 3.0 [5][8]. Group 3: Challenges in AI Processor Design - Key challenges in designing AI processors include the lengthy time required to construct AI computing architectures, the prolonged development of instruction systems, and the long cycles for compiling software [9]. - Achieving widespread ecosystem support for self-built instruction systems presents significant hurdles [9]. Group 4: RISC-V and EVAS Architecture - RISC-V's open and modular design allows for the customization of AI acceleration instruction sets, making it a suitable foundation for DSA [8]. - The introduction of the Virtual Instruction Set Architecture (VISA) aims to bridge the gap between AI compilers and backend compilation, enhancing performance optimization [10][11]. - The EVAS architecture integrates VISA with RISC-V microinstructions, ensuring efficient execution of AI computations while improving user programming experience [12][16]. Group 5: Upcoming Innovations - The upcoming chip from the company will support various data types, including INT4, INT8, FP8, FP16, and BF16, with a focus on mixed-precision computing [17]. - The new architecture aims to provide advanced computing solutions for applications in autonomous driving, embodied intelligence, and other edge-cloud industry applications, contributing to the progress towards AGI [17].