面板级封装的兴起

Core Insights - The demand for logic-to-memory integration driven by AI and high-performance computing is propelling advancements in panel-level packaging (PLP), with expectations that PLP will approach 10 times the maximum reticle size in the coming years [2][3] - Fan-out panel-level packaging (FOPLP) is emerging as a cost-effective solution, replacing silicon interposers with organic interposers, which is crucial for accommodating larger chip sizes and higher I/O counts [2][3][20] - The panel-level packaging market is projected to grow significantly, from $160 million in 2024 to $650 million, and nearly tripling to approximately $2.2 billion by 2030 [4] Panel-Level Packaging Developments - The integration of organic interposers and glass substrates is advancing, with companies like TSMC transitioning from wafer-based to panel-based processes for advanced packaging [3][4] - The choice of panel size varies based on application needs, with sizes ranging from 310 x 310 mm to 700 x 700 mm, influenced by existing manufacturing capabilities [5][6] - The utilization efficiency of panel-level packaging improves with larger interposer sizes, significantly reducing waste compared to wafer-level processes [6][10] Manufacturing Techniques and Challenges - Various manufacturing processes are being implemented in fan-out packaging, including chip-first, RDL-first, and mold-first methods, each with its own advantages and challenges [12][14] - Warpage remains a critical issue in fan-out packaging, exacerbated by differences in thermal expansion coefficients between materials, necessitating new materials and process controls to mitigate this risk [16][18][20] - Laser direct imaging and step-and-repeat lithography are both utilized for RDL patterning, with step-and-repeat lithography being more suitable for high throughput [10][20] Future Outlook - The future of panel-level packaging is promising, particularly for AI and HPC devices, as manufacturers seek to achieve yield rates comparable to current fan-out wafer-level packaging processes [20] - The development of new interlayer dielectric materials and molding materials with thermal expansion coefficients closer to silicon will enhance control over chip displacement and warpage [20]