Core Viewpoint - The demand for Chiplet architecture is increasing due to advancements in cloud computing, high-performance computing (HPC), and artificial intelligence (AI), alongside rising technical challenges and costs in semiconductor design and manufacturing [1][3]. Group 1: UCIe Alliance and Standards - The Universal Chiplet Interconnect Express (UCIe) Alliance was established in 2022 by major semiconductor companies and cloud service providers to create standardized interconnect specifications for Chiplets, enhancing flexibility, efficiency, and customization [1]. - UCIe 3.0 was recently launched, featuring enhancements in power efficiency and management while maintaining backward compatibility, and it supports data rates of 48 GT/s and 64 GT/s, doubling the bandwidth of the previous UCIe 2.0 [3][5]. Group 2: Performance and Applications - The performance improvements in UCIe 3.0 are particularly aimed at meeting the "insatiable demand for high bandwidth" in rapidly expanding fields such as AI, HPC, and data analytics, where interconnect boundary lengths are limited [3][5]. - The new data rates apply to both UCIe-S (2D standard packaging) and UCIe-A (2.5D advanced packaging) designs, addressing the need for higher throughput within constrained interconnect boundaries [5][9]. Group 3: Technical Specifications - UCIe 3.0 introduces new data rates of 48 GT/s and 64 GT/s, with specific characteristics for UCIe-S and UCIe-A, including bandwidth density and power efficiency targets [9]. - The standard maintains backward compatibility to ensure seamless integration with existing systems and infrastructure, allowing for a smooth transition for system designers and developers [7][9]. Group 4: Broader Implications - The Chiplet architecture is becoming ubiquitous across various sectors, including mobile devices, PCs, and automotive applications, with UCIe expected to cover a complete computing continuum from handheld devices to data centers [10]. - UCIe 3.0 also includes improvements such as runtime recalibration for low-power link tuning and more flexible Session Initiation Protocol (SIP) topologies, enhancing its applicability in new interconnect scenarios [10].
UCIe 3.0来了:Chiplet互连速度翻倍