势银观察 | 晶圆级封装向面板级封装过渡的产业化挑战

Core Viewpoint - The article discusses the commercialization and development stages of panel-level packaging (PLP) technology, highlighting its potential advantages over traditional wafer-level packaging (WLP) and the challenges it faces in the industry [2][3][6]. Group 1: Panel-Level Packaging Development - Panel-level packaging is currently in the industry cultivation stage, focusing on application scenario development, with the first phase targeting discrete devices and power SiP adopting PLP technology [3]. - The second phase involves the integration of mixed-signal multi-chip packaging into PLP technology, primarily for consumer electronics and IoT products [3]. - The final phase will see the introduction of memory-compute integrated chips using PLP technology, expected to commence in 3-5 years, marking the competitive phase against wafer-level 2.5D/3D packaging [3]. Group 2: Technical and Operational Challenges - Panel-level packaging faces high operational costs, poor technical stability, and an incomplete industrial ecosystem, which are significant barriers to its widespread adoption [6]. - The large size of the panels complicates the chip placement and bonding processes, increasing the difficulty of controlling displacement, line width, and stress [6]. - Establishing a panel-level packaging ecosystem requires new equipment and material supply chains, which necessitates substantial investment, particularly in high-end memory-compute integrated chip sectors [6]. Group 3: Upcoming Events and Industry Collaboration - TrendBank plans to host the Heterogeneous Integration Annual Conference from November 17-19, 2025, in Ningbo, focusing on advanced packaging technologies and fostering collaboration between industry and academia [7]. - The conference will cover core technologies such as multi-material heterogeneous integration, optoelectronic co-packaging, and advanced packaging techniques like TGV and FOPLP [7].