半导体行业观察·2025-09-26 01:11Core Viewpoint - The strategic alliance between NVIDIA and Intel aims to integrate AI-accelerated computing with the advantages of the x86 ecosystem, focusing on the NVLink technology architecture, which poses a significant challenge to the long-dominant PCIe standard [2][3] Group 1: NVLink vs PCIe - NVLink offers several times the bandwidth and lower latency compared to PCIe, making it superior for AI training and large-scale computing, thus threatening the PCIe technology route [2][3] - Intel's embrace of NVLink is symbolically significant, indicating a potential restructuring of CPU and GPU interconnect paradigms, which may impact the Retimer chip market that relies on PCIe [2][3] Group 2: Retimer Chips - Retimer chips are essential for addressing signal integrity issues in PCIe connections, especially as data transfer rates increase with newer PCIe versions [5][6] - The demand for Retimer chips is expected to rise significantly due to the expansion of cloud computing and AI servers, where multiple GPUs are used, necessitating 8 to 16 Retimer chips per AI server [10][11] Group 3: Market Dynamics - The Retimer chip market is characterized by a "duopoly" led by AsteraLabs and Lanqi Technology, with competition from traditional analog giants and other players [12][13] - The global PCIe Retimer chip market is projected to reach $1.8 billion by 2025, driven by the increasing need for high-speed interconnects in AI and server applications [15] Group 4: Impact of NVIDIA and Intel Alliance - The collaboration between NVIDIA and Intel may disrupt the Retimer chip market, as NVLink's superior bandwidth and lower latency could reduce the need for signal compensation chips [17][19] - If Intel's CPUs begin to support NVLink, it could accelerate the adoption of NVLink as a standard, further diminishing the role of Retimer chips in the ecosystem [19][20] Group 5: Future Outlook - Despite the potential challenges posed by NVLink, Retimer chips may still hold value in scenarios where long-distance transmission and complex topologies are involved, ensuring data integrity in non-GPU device interconnections [23]