二维晶体管路线图

Core Viewpoint - The article discusses the transition of two-dimensional (2D) semiconductors from a long-term development prospect to a core technology in the semiconductor industry, driven by the limitations of current silicon-based technologies and the need for advanced gate stack engineering for commercialization [1][5]. Group 1: Two-Dimensional Semiconductors - Two-dimensional semiconductors are gaining attention as channel materials that can maintain electrical properties even at atomic thickness, making them a promising alternative to silicon [1][8]. - Leading semiconductor companies and research institutions, including Samsung, TSMC, and Intel, have incorporated 2D semiconductor transistors into their technology roadmaps for the post-silicon era [1][5]. - The commercialization of 2D semiconductors faces significant challenges, particularly in gate stack integration technology, which is crucial for device performance and stability [1][5]. Group 2: Gate Stack Engineering - The research team from Seoul National University has developed a comprehensive roadmap for gate stack engineering, which is essential for the next generation of semiconductor devices [2][4]. - The study categorizes gate stack integration methods into five types: van der Waals (vdW) dielectrics, vdW-oxidized dielectrics, quasi-vdW dielectrics, vdW-seeded dielectrics, and non-vdW-seeded dielectrics, each evaluated based on various performance metrics [3][4]. - The potential application of ferroelectric materials in gate stack technology is highlighted, which could lead to ultra-low power logic, non-volatile memory, and memory computing [3][4]. Group 3: Performance Metrics and Challenges - Key performance indicators for gate stack engineering include subthreshold swing (SS), on-state current density, power supply voltage, and threshold voltage (VT), which are influenced by the composition and quality of the gate stack [6][12]. - The International Roadmap for Devices and Systems (IRDS) emphasizes the need for 2D semiconductors to meet specific performance targets, such as reducing equivalent oxide thickness (EOT) to below 0.5 nm by 2031 [12][29]. - Achieving low interface trap density (Dit) is critical for enhancing gate stack performance and controlling short-channel effects, which are essential for the scalability of 2D transistors [12][13][28]. Group 4: Integration Strategies - Various integration strategies for gate stacks are explored, focusing on minimizing Dit and leakage current while optimizing EOT [14][19]. - The article discusses the challenges of integrating high-k dielectrics with 2D semiconductors due to their surface chemical inertness and the need for tailored deposition methods [14][19]. - The potential of hybrid gate stack structures, which combine vdW and non-vdW dielectrics, is presented as a promising solution for achieving CMOS compatibility and reliability [20][21]. Group 5: Future Directions - The development of ferroelectric embedded gate stacks in 2D transistors is seen as a promising avenue for integrating logic and memory functions into single devices, enhancing performance and reducing power consumption [30][31]. - The article emphasizes the importance of optimizing materials and processes for gate stack integration to meet the demands of advanced CMOS technology [22][23]. - Continuous advancements in interface engineering and the development of specialized materials for 2D semiconductors are crucial for unlocking their full potential in next-generation electronic applications [22][30].