CMOS 2.0，来了

Core Viewpoint - The article discusses the advancements in semiconductor technology, particularly the breakthroughs achieved by imec in wafer-to-wafer hybrid bonding and back interconnects, paving the way for CMOS 2.0 technology set to launch in 2024 [1]. Group 1: CMOS 2.0 Technology Core - CMOS 2.0 technology focuses on advanced 3D interconnects and back power delivery networks (BSPDN), enabling high-density connections on both sides of the wafer [2]. - Key milestones presented at the 2025 VLSI symposium include wafer-to-wafer hybrid bonding with a spacing of 250 nanometers (nm) and a back spacing of 120 nm for through-die vias (TDV), addressing performance bottlenecks in AI and mobile applications [2]. Group 2: Wafer-to-Wafer Hybrid Bonding - Wafer-to-wafer hybrid bonding allows for sub-micron spacing, facilitating high bandwidth and low power signal transmission [3]. - The optimized process includes aligning and bonding two processed wafers at room temperature, achieving reliable connections with a spacing of 400 nm using silicon carbon nitride (SiCN) [3]. - imec has reduced bonding spacing to 300 nm with 95% of chip alignment errors under 25 nm, showcasing the feasibility of 250 nm spacing bonding under a hexagonal pad grid architecture [3]. Group 3: Back Interconnect Technology - Back interconnect technology complements front bonding by enabling "front-back" connections through nano-scale silicon vias (nTSV) or direct contact [4]. - This technology allows seamless integration of metal layers on both sides of the wafer, reducing voltage drop and alleviating signal routing congestion in the front-end [4]. - imec demonstrated a back dielectric via (TDV) with a bottom diameter of 20 nm and a spacing of 120 nm, balancing the need for fine spacing connections on both sides of the wafer [4]. Group 4: Advantages of Back Power Delivery Network (BSPDN) - BSPDN enhances CMOS 2.0 performance by relocating power distribution to the back of the wafer, accommodating wider and lower-resistance interconnects [6]. - Research indicates that BSPDN improves power, performance, area, and cost (PPAC) metrics for "always-on" designs and is particularly beneficial for "switch domain" architectures in mobile SoCs [6]. - In 2 nm mobile processor designs, BSPDN reduced voltage drop by 122 millivolts (mV), leading to a 22% area savings while enhancing performance and energy efficiency [6]. Group 5: Technology Implementation and Future Outlook - Supported by pilot lines in nano integrated circuits (NanoIC) and EU funding, these breakthroughs are transitioning CMOS 2.0 from concept to practical application [7]. - The future collaboration with equipment suppliers will be crucial as bonding spacing shrinks below 200 nm to address alignment challenges [7]. - High-density front and back interconnect technologies are expected to usher in a new era of computing innovation, meeting diverse application demands for performance, power, and integration [7].