二维晶体管路线图

Core Insights - The article discusses the transition of 2D semiconductors from a long-term development prospect to a core technology in the semiconductor industry, particularly as the industry moves beyond silicon technology in the mid-2030s [1][4]. Group 1: 2D Semiconductor Technology - 2D semiconductors are gaining attention as they maintain electrical properties even at atomic thickness, making them suitable for future semiconductor applications [1][8]. - Major semiconductor companies and research institutions, including Samsung, TSMC, and Intel, are incorporating 2D semiconductor transistors into their technology roadmaps [1][4]. - The commercialization of 2D semiconductors faces challenges, particularly in gate stack integration technology, which is crucial for device performance and stability [1][4]. Group 2: Gate Stack Engineering - The research team from Seoul National University has developed a comprehensive roadmap for "gate stack engineering," a core technology for 2D transistors [2][4]. - The study categorizes gate stack integration methods into five types: van der Waals dielectrics, vdW-oxidized dielectrics, quasi-vdW dielectrics, vdW-seeded dielectrics, and non-vdW-seeded dielectrics, each evaluated based on various performance metrics [3][4]. - The potential of ferroelectric materials in gate stack technology is highlighted, enabling ultra-low power logic and non-volatile memory applications [4][30]. Group 3: Performance Metrics and Challenges - Key performance indicators for gate stack engineering include subthreshold swing (SS), on-current (I_on), leakage current density (J_leak), threshold voltage (V_T), and power supply voltage (V_dd) [12][22]. - The International Roadmap for Devices and Systems (IRDS) sets ambitious targets for these metrics, such as achieving an equivalent oxide thickness (EOT) below 0.5 nm and a leakage current density below 0.01 A cm^-2 by 2031 [12][24]. - The article emphasizes the need for continuous development in interface engineering and material selection to meet these performance goals and ensure CMOS compatibility [12][29]. Group 4: Future Directions - The integration of ferroelectric materials into gate stacks is seen as a promising direction for developing advanced electronic technologies, including AI semiconductors and ultra-low power mobile chips [4][30]. - The research indicates that overcoming the challenges of high-quality gate stack integration is crucial for the commercialization of 2D transistors, with plans for collaboration between academia and industry to advance device-level integration [4][30].