DRAM，突破10nm

Core Viewpoint - Samsung and its Advanced Technology Research Institute announced a new DRAM technology for manufacturing below 10nm, utilizing a Cell-on-Peri (CoP) architecture that stacks memory cells on top of peripheral circuits, enhancing storage density and efficiency while addressing high-temperature challenges [1][2]. Group 1: Technology Overview - The new CoP architecture differs from traditional methods by placing the surrounding transistors above the memory cells, which mitigates damage during high-temperature stacking processes [1]. - Samsung's technology is named "High-Temperature Resistant Amorphous Oxide Semiconductor Transistor for CoP Vertical Channel DRAM below 10nm" [1]. - The vertical channel transistors, with a channel length of 100nm, can withstand temperatures up to 550 degrees Celsius, maintaining performance stability [2]. Group 2: Performance and Stability - In high-temperature and high-pressure tests, the threshold voltage drift was only -8mV, indicating a stable operational lifespan exceeding 10 years [2]. - The high thermal stability of the transistors is attributed to their ability to suppress ion migration at the channel-electrode interface [2]. - During aging tests, the transistors exhibited minimal degradation in drain current, demonstrating robust performance [2]. Group 3: Development Stage and Future Applications - The technology is currently in the research and development phase and is expected to be applied in future DRAM processes below 10nm (0a and 0b nodes) [2].