这项技术，颠覆芯片堆叠

Core Insights - MIT researchers have developed a new solution to address energy consumption issues in data transfer between logic circuits and memory, proposing a stacked structure that integrates logic and memory transistors in the backend of traditional CMOS chips [1][2][8] Group 1: Research Findings - The new architecture involves adding active device layers in the backend of the chip, allowing for a compact vertical stack that reduces energy and time consumption during data transfer [1][2] - The key device in this stack is a BEOL transistor with an amorphous indium oxide channel layer, which can be "grown" at approximately 150°C, preventing damage to underlying circuits [2][10] - The integration of ferroelectric hafnium zirconium oxide (HZO) layers has resulted in BEOL transistors with a switching speed of 10 nanoseconds and a size of about 20 nanometers, achieving low operating voltage compared to similar devices [4][11] Group 2: Manufacturing Process - The manufacturing process focuses on controlling defects in the indium oxide layer, which is only about 2 nanometers thick, optimizing it to ensure fast and clean switching of transistors [4][11] - The new method allows for the stacking of active components without the high temperatures typically required in front-end processes, thus preserving existing components [2][10] Group 3: Applications and Future Directions - This technology is expected to significantly benefit workloads dominated by memory traffic, such as AI inference and deep learning, by reducing energy consumption in data-centric computing [6][9] - Future plans include integrating backend storage transistors into single circuits and further optimizing the control of ferroelectric layer properties [12]