自研224 Gb/s SerDes，思科这颗芯片太猛了

Core Viewpoint - The article discusses the advancements in Cisco's networking technology, particularly the introduction of the G300 ASIC chip, which aims to enhance data center interconnectivity and performance for AI and high-performance computing (HPC) applications [2][3][5]. Group 1: G300 ASIC Chip Features - The G300 ASIC chip offers an aggregate bandwidth of 102.4 Tb/s and is designed to compete with Broadcom and NVIDIA for market share in high-speed port connections [2][5]. - It features a unified buffer of 252 MB shared among 512 SerDes circuits, improving efficiency and reducing packet loss during network congestion [10][12]. - The chip supports various configurations, allowing for the creation of switches with different port counts and speeds, such as 512 ports at 200 Gb/s or 64 ports at 1.6 Tb/s [12][13]. Group 2: Comparison with Previous Models - The G300 is positioned as a significant upgrade over the G200, with a 33% higher network utilization and a 28% faster job completion rate [14]. - Despite potentially being three to four times the price of the G200, the G300 is considered cost-effective due to its enhanced capabilities and efficiency [21]. Group 3: Technological Innovations - The G300 utilizes a "no-cover" chip design for better heat dissipation and is manufactured using advanced processes from TSMC, including 3 nm and 4 nm technologies [7][8]. - It can directly drive linear pluggable optical modules (LPO), which can reduce power consumption by approximately 50%, contributing to a 30% reduction in overall power usage for AI infrastructure [13][21]. Group 4: Market Implications - The advancements in the G300 chip are expected to address the growing demands of AI workloads, with companies needing higher bandwidth to support upcoming GPU and XPU releases [13][21]. - Cisco's testing and certification processes for optical modules are highlighted as being more comprehensive than competitors, which is crucial for maintaining performance in AI workloads [15].