日本2nm,锁定2028量产
半导体芯闻·2026-02-12 10:37

Core Viewpoint - Rapidus plans to start mass production of 2nm chips in the second half of FY2027, with full-scale production expected to begin in FY2028, aiming to quadruple its production capacity in the first year of operation [1]. Group 1: Production Plans - The company will manufacture chips at its factory in Chitose, Hokkaido, which will handle both front-end wafer manufacturing and back-end processes such as cutting and packaging [1]. - Initial monthly production capacity is set at 6,000 wafers, with plans to increase this to approximately 25,000 wafers within the following year [1]. Group 2: Technological Challenges - Advanced semiconductor production requires the introduction of over 200 production equipment, with achieving high yield rates being the biggest challenge for the company [1]. - Yield levels directly impact chip performance and production costs, making it crucial for Rapidus to maintain high yield rates to ensure profitability [1]. Group 3: Market Demand and Client Stability - As a foundry, Rapidus must secure stable customer orders to maintain factory utilization rates, which is a core challenge for its expansion plans [1][3]. - The ability to achieve high yield rates and consistently attract customer orders will be critical for the company's success in scaling production [3]. Group 4: Technological Innovations - The company is focusing on Chiplet technology, which integrates different types of chips on the same substrate, and aims to enhance back-end automation technology for high-performance advanced semiconductors [2]. - Rapidus plans to launch a back-end pilot line this spring to mount chips onto electronic substrates, indicating a commitment to seamless integration of front-end and back-end processes [2]. Group 5: Industry Collaborations - NVIDIA has been collaborating with several companies, including Rapidus, to expand the application of GPU acceleration in semiconductor manufacturing beyond just lithography, now including defect detection and material design simulation [2].